参数资料
型号: ISL6532AEVAL1
厂商: Intersil
文件页数: 4/9页
文件大小: 0K
描述: EVALUATION BOARD 1 ISL6532A
标准包装: 1
主要目的: 特殊用途 DC/DC,DDR 存储器电源
输出及类型: 3,非隔离
输出电压: 1.25V,1.5V,2.5V
输入电压: 5V,12V
稳压器拓扑结构: 降压
频率 - 开关: 250kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6532A
Application Note 1056
ISL6532AEVAL1 Customization
2.480V
V DDQ
50mV/DIV
V TT
50mV/DIV
There are numerous ways in which a designer might modify
the ISL6532AEVAL1 evaluation board for differing
requirements. Some of the changes which are possible
include:
1.230V
1.480V
V AGP
50mV/DIV
V DDQ Load
10A/DIV
V TT Load
2A/DIV
200 μ s/DIV
FIGURE 9. SOURCING TRANSIENTS ON V DDQ AND V TT
V DDQ
50mV/DIV
2.480V
? The input and output inductors, L1 and L2
? The input and output capacitance for any of the three
regulators.
? The overcurrent trip point, programmed through the
OCSET resistor, R7
? By changing the value of C19, the soft start profile of the
V TT rail, when transitioning from Sleep to Active State
? All MOSFET footprints on the evaluation board allow for
either SO8 or PowerPak packaged MOSFETs to be
utilized
? The 3.3VSBY LDO, Ux1, may be circumvented by
shorting pins 2 and 3 together. This will provide the V DDQ
standby LDO with 5V while in Sleep state, which allows
the load to be increased by 100mA.
1.230V
1.480V
V TT
50mV/DIV
V AGP
50mV/DIV
V AGP Load
1A/DIV
200 μ s/DIV
FIGURE 10. TRANSIENTS ON 1.5V AGP RAIL
Conclusion
The ISL6532AEVAL1 is a versatile platform that allows
designers to gain a full understanding of the functionality of
the ISL6532A in a DDR Memory System. The board is also
flexible enough to allow the designer to modify the board for
differing requirements.
References
For Intersil documents available on the web, see
http://www.intersil.com/
[1] ISL6532A Data Sheet, Intersil Corporation, File No.
FN9099.
Efficiency
Figure 11 shows the efficiency of the VDDQ regulator while
in Active (S0) State. As the other regulated outputs are all
derived through linear regulation, their efficiencies are not
shown.
96%
94%
92%
90%
88%
86%
84%
82%
0
5
10
15
20
LO A D C UR R E N T [ A ]
FIGURE 11. V DDQ EFFICIENCY
4
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