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参数资料
| 型号： | ISL6532BCRZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/15页 |
| 文件大小： | 0K |
| 描述： | IC REG/CTRLR ACPI DUAL DDR 20QFN |
| 标准包装： | 4,000 |
| 应用： | 存储器，DDR/DDR2 稳压器 |
| 电流 - 电源： | 5.25mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN 裸露焊盘（6x6） |
| 包装： | 带卷 (TR) |
ISL6532B
OSC
DRIVER
V IN
Compensation Break Frequency Equations
F Z1 = ------------------------------------
F P1 = ---------------------------------------------------------
2 π x R 2 x ? ---------------------- ?
? V OSC
PWM
COMPARATOR
-
+
DRIVER
L O
PHASE
C O
V DDQ
1
2 π x R 2 x C 2
1
? C 1 x C 2 ?
? C 1 + C 2 ?
F Z2 = -------------------------------------------------------
F P2 = ------------------------------------
Z FB
ESR
(PARASITIC)
1
2 π x ( R 1 + R 3 ) x C 3
1
2 π x R 3 x C 3
V E/A
Figure 6 shows an asymptotic plot of the DC-DC converter’s
-
+
ERROR
AMP
Z IN
REFERENCE
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
DETAILED COMPENSATION COMPONENTS
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
C 2
C 1
R 2
Z FB
C 3
Z IN
R 3
V DDQ
gain. Check the compensation gain at FP2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 6 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
V DDQ = 0.8 × ? 1 + ------ 1 - ?
COMP
-
+
ISL6532B
REFERENCE
? R ?
? R 4 ?
FB
R 4
R 1
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
100
F Z1 F Z2
F P1
F P2
The compensation network consists of the error amplifier
80
(internal to the ISL6532B) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
60
40
20
20LOG
(R 2 /R 1 )
OPEN LOOP
ERROR AMP GAIN
20LOG
is the difference between the closed loop phase at f 0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R 1 , R 2 ,
0
-20
MODULATOR
GAIN
(V IN / ? V OSC )
COMPENSATION
GAIN
R 3 , C 1 , C 2 , and C 3 ) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
-40
-60
10
100
1K
F LC
10K
F ESR
100K
1M
CLOSED LOOP
GAIN
10M
2. Place 1 ST Zero Below Filter’s Double Pole (~75% F LC ).
3. Place 2 ND Zero at Filter’s Double Pole.
4. Place 1 ST Pole at the ESR Zero.
5. Place 2 ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Output Voltage Selection
The output voltage of the VDDQ PWM converter can be
programmed to any level between VIN and the internal
reference, 0.8V. An external resistor divider is used to scale
the output voltage relative to the reference voltage and feed
it back to the inverting input of the error amplifier, see
Figure 6.
11
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