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参数资料
| 型号： | ISL6539EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 20/20页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 1 FOR ISL6539 |
| 标准包装： | 1 |
| 系列： | * |
ISL6539
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
N
M28.15
INDEX
AREA
E
-B-
H
0.25(0.010) M
GAUGE
PLANE
B M
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
1
2
3
A
0.053
0.069
1.35
1.75
-
-A-
D
SEATING PLANE
A
0.25
0.010
h x 45°
L
A1
A2
B
0.004
-
0.008
0.010
0.061
0.012
0.10
-
0.20
0.25
1.54
0.30
-
-
9
C
0.007
0.010
0.18
0.25
-
e
B
0.17(0.007) M
-C-
C A M
B S
A1
α
0.10(0.004)
A2
C
D
E
e
H
h
0.386 0.394
0.150 0.157
0.025 BSC
0.228 0.244
0.0099
0.0196
9.81 10.00
3.81 3.98
0.635 BSC
5.80 6.19
0.26
0.49
3
4
-
-
5
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
3. Dimension “D” does not include mold flash, protrusions or gate
L
N
α
0.016
0°
28
0.050
8°
0.41
0°
28
1.27
8°
6
7
-
Rev. 1 6/04
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual in-
dex feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN9144.6
April 29, 2010
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