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| 型号： | ISL6539IAZ |
| 厂商： | Intersil |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR DDR DRAM, SDRAM 28QSOP |
| 标准包装： | 48 |
| 应用： | 控制器，DDR DRAM，SDRAM |
| 输入电压： | 3.3 V ~ 18 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 28-SSOP/QSOP |
| 包装： | 管件 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
ISL6539
TABLE 1. PWM COMPARATOR RAMP AMPLITUDE FOR
DUAL SWITCHER APPLICATION
VRAMP
accommodate many applications having a wide range of
parameters. The schematic for the internal compensator is
shown in Figure 8.
VIN PIN CONNECTIONS
AMPLITUDE
Ch1 and Ch2 Input Voltage Input voltage > 4.2V
Input voltage < 4.2V
V IN /8
1.25V
1.25pF
500k
+
GND 1.25V
TABLE 2. PWM COMPARATOR RAMP VOLTAGE AMPLITUDE
FOR DDR APPLICATION
TO PWM
COMPARATOR
4.4k
ISEN
1M 16.7pF
-
Vc
0.9V
300k
VSEN
VRAMP
VIN PIN CONNECTION
AMPLITUDE
Ch1
Input Voltage
Input voltage > 4.2V
V IN /8
FIGURE 8. THE INTERNAL COMPENSATOR
Input voltage < 4.2V
1.25V
1.857 ? 10 ? --------------- + 1 ? ? --------------- + 1 ?
? 2 π f ? ? 2 π f ?
Gcomp ( s ) = ---------------------------------------------------------------------------------------------
s ? -------------- + 1 ?
? 2 π f ?
Ch2
GND
Input voltage >4.2V
GND
1.25V
0.625V
1.25V
Its transfer function can be written as Equation 11:
5 s s
z1 z2
p1
(EQ. 11)
The small signal transfer function from the error amplifier
output voltage V c to the output voltage V o can be written in
Equation 7:
where:
f z1 = 6.98kHz, f z2 = 380kHz, and f p1 = 137kHz
? --------- + 1 ?
G ( s ) = G m --------------------------------------- ---------------------------------------------------------
R i + DCR + R o ? s ? ? s ?
? Wp1
? ? Wp2
?
s
R o ? Wz ?
------------- + 1 ------------- + 1
(EQ. 7)
Outside the ISL6539 chip, a capacitor C z can be placed in
parallel with the top resistor in the feedback resistor divider,
as shown in Figure 6. In this case the transfer function from
the output voltage to the middle point of the divider can be
The DC gain is derived by shorting the inductor and opening
written as:
R 2 sR 1 C z + 1
R 1 + R 2 s ( R 1 || R 2 ) C z + 1
the capacitor. There is one zero and two poles in this transfer
function.
The zero is related to ESR and the output capacitor.
Gfd ( s ) = --------------------- ----------------------------------------------
(EQ. 12)
The first pole is a low frequency pole associated with the
output capacitor and its charging resistors. The inductor can
be regarded as short. The second pole is the high frequency
pole related to the inductor. At high frequency the output cap
can be regarded as a short circuit. By approximation, the
poles and zero are inversely proportional to the time
constants, associated with inductor and capacitor, by
Equations 8, 9 and 10:
The ratio of R 1 and R 2 is determined by the output voltage
set point; therefore, the position of the pole and zero
frequency in Equation 12 may not be far apart; however,
they can improve the loop gain and phase margin with the
proper design.
The C z can bring the high frequency transient output voltage
variation directly to the VSEN pin to cause the PGOOD drop.
Such an effect should be considered in the selection of C z .
Wz = ------------------------
1
ESR*C o
(EQ. 8)
From the analysis in Equation 12, the system loop gain can
be written as Equation 13:
Wp1 = -------------------------------------------------------------------------------
1
( ESR + ( R i + DCR ) || R o ) *C o
(EQ. 9)
Gloop ( s ) = G ( s ) ? Gcomp ( s ) ? Gfd ( s )
(EQ. 13)
R i + DCR + ESR || R o
L o
Wp2 = ----------------------------------------------------------
(EQ. 10)
Figure 9 shows the composition of the system loop gain. As
shown in the graph, the power stage became a well damped
second order system compared to the LC filter
Since the current loop separates the LC resonant poles into
two distant poles, and ESR zero tends to cancel the high
frequency pole, the second order system behaves like a first
order system. This control method simplifies the design of
the internal compensator and makes it possible to
11
characteristics. The ESR zero is so close to the high
frequency pole that they cancel each other out. The power
stage behaves like a first order system. With an internal
compensator, the loop gain transfer function has a cross
over frequency at about 30kHz. With a given set of
parameters, including the MOSFET r DS(ON) , current sense
FN9144.6
April 29, 2010
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6539IAZ-T | 功能描述:电流型 PWM 控制器 ISL6539 DL SWITCHER 15V INDUSTRIAL GRD RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6540ACRZ | 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
| ISL6540ACRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 特色产品:LM3753/54 Scalable 2-Phase Synchronous Buck Controllers 标准包装:1 系列:PowerWise® PWM 型:电压模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.5 V ~ 18 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-5°C ~ 125°C 封装/外壳:32-WFQFN 裸露焊盘 包装:Digi-Reel® 产品目录页面:1303 (CN2011-ZH PDF) 其它名称:LM3754SQDKR |
| ISL6540ACRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL6540ACRZ-T W/GOLD BOND WIRE ONLY - Tape and Reel |
| ISL6540AIRZ | 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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