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| 型号： | ISL65426EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 18/22页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 1 FOR ISL65426 |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 1 |
| 系列： | * |
ISL65426
load device. Individual power-good indicators provide
options for linking to external system monitors.
Undervoltage Protection
Separate hysteretic comparators monitor the feedback pin
(FB) of each converter channel. The feedback voltage is
compared to a set undervoltage (UV) threshold based on the
output voltage selected. Once one of the comparators trip
indicating a valid UV condition, a 4-bit UV counter
increments. If both channel comparators detect an UV
condition during the same switching cycle, the 4-bit counter
increments twice. Once the 4-bit counter overflows, the UV
protection logic shuts down both regulators.
The comparator is reset if the feedback voltage rises back
up above the UV threshold plus a specified amount of
hysteresis outlined in the “Electrical Specifications” table. If
both converter channels experience an UV condition and
one rises back within regulation, then the counter continues
to progress toward overflow.
Overvoltage Response
If the output voltage exceeds the overvoltage (OV) level for
the power-good signal, the controller will fight this condition
by actively trying to regulate the output voltage back down to
the reference level. This method of fighting the rise in output
voltage is limited by the reverse current capability of the total
number of power blocks associated with the output. The
approximate reverse current capability of each power block
is 0.5A. The power-good signal will drop indicating the
output voltage is out of specification. This signal will not
transition high again until the output voltage has dropped
below the falling PGOOD OV threshold.
Overcurrent Protection
A pilot device is integrated into the upper device structure of
each master power block. The pilot device samples current
through the master power block upper device each cycle. This
channel current feedback is scaled based on the state of the
ISET1 and ISET2 pins. The channel current information is
compared to an overcurrent (OC) limit based on the power
block configuration. Each 1A power block tied to the master
power block increases the OC limit by 2A. For example, if
both masters have two slaves associated with each of them
then the OC limit for each output is 6A for a 3A configuration.
If the sampled current exceeds the OC threshold, a 4-bit OC
up/down counter increments by one LSB. If the sampled
current falls below the OC threshold before the counter
overflows, the counter is reset. If both regulators experience
an OC event during the same cycle, the counter increments
twice. Once the OC counter reaches 1111, both channels are
shutdown. If both channels fall below the overcurrent limit
during the same cycle, the OC counter is reset.
Once in shutdown, the controller enters a delay interval,
equivalent to the SS interval, allowing the die to cool. The
OC counter is reset entering the delay interval. The
18
protection logic initiates a normal SS internal once the delay
interval ends. If the outputs both successfully soft-start, the
power-good signal goes high and normal operation
continues. If OC conditions continue to exist during the SS
interval, the OC counter must overflow before the controller
shutdowns both outputs again. This hiccup mode continues
indefinitely until both outputs soft-start successfully.
Note: It is recommended to add a Schottky diode of
adequate rating from LX1 to PGND and from LX5 to PGND
to avoid severe negative ringing that can disturb the OC
counter.
Thermal Monitor
Thermal-overload protection limits total power dissipation in
the ISL65426. An internal thermal sensor monitors die
temperature continuously. If controller junction temperature
exceeds +150 °C , the thermal monitor commands the POR
circuitry to shutdown both channels and latch-off. The POR
latch is reset by cycling VCC to the controller.
Component Selection Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a power
converter. It is assumed that the reader is familiar with many
of the basic skills and techniques referenced in the following.
In addition to this guide, Intersil provides a complete
reference design that includes schematics, a bill of materials
and example board layout.
Output Filter Design
The output inductor and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase node. The output filter also must
provide the transient energy until the regulator can respond.
Due to its inherent low bandwidth as compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
OUTPUT CAPACITOR SELECTION
The critical load parameters in choosing the output capacitors
are the maximum size of the load step ( Δ I), the load-current
slew rate (di/dt), and the maximum allowable output voltage
deviation under transient loading ( Δ V MAX ). Capacitors are
characterized according to their capacitance, ESR (Equivalent
Series Resistance), and ESL (Equivalent Series Inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. Neglecting the contribution of inductor current and
FN6340.3
March 25, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL65426EVAL3Z | 制造商:Intersil Corporation 功能描述: |
| ISL65426HRZ | 功能描述:IC REG BUCK SYNC ADJ 6A DL 50QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:两者兼有 输出数:1 输出电压:5V，1 V ~ 10 V 输入电压:3.5 V ~ 28 V PWM 型:电流模式 频率 - 开关:220kHz ~ 1MHz 电流 - 输出:600mA 同步整流器:无 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-SSOP（0.154"，3.90mm 宽） 包装:带卷 (TR) 供应商设备封装:16-QSOP |
| ISL65426HRZS2698 | 制造商:Intersil Corporation 功能描述:LEAD-FREE W/ANNEAL, DUAL BUCK REGULATOR. -10 TO +100 TEMP. - Rail/Tube 制造商:Intersil 功能描述:W/ANNEAL DL BUCKG -10 TO +100 TEMP |
| ISL65426HRZS2715 | 制造商:Intersil Corporation 功能描述:S SPEC FOR TRACKING BROADCOM BUSINESS ONLY-SOLD THRU DISTI - Rail/Tube |
| ISL65426HRZ-T | 功能描述:IC REG BUCK SYNC ADJ 6A DL 50QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:两者兼有 输出数:1 输出电压:5V，1 V ~ 10 V 输入电压:3.5 V ~ 28 V PWM 型:电流模式 频率 - 开关:220kHz ~ 1MHz 电流 - 输出:600mA 同步整流器:无 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-SSOP（0.154"，3.90mm 宽） 包装:带卷 (TR) 供应商设备封装:16-QSOP |
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