参数资料
型号: ISL6559CB-T
厂商: Intersil
文件页数: 15/21页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 28-SOIC
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 4MHz
占空比: 75%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
ISL6559
loop. Select the values for these resistors based on the room
temperature r DS(ON) of the lower MOSFETs; the full-load
operating current, I FL ; and the number of phases, N
according to Equation 19 (see also Figure 3).
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
R ISEN = ----------------------- )
I FL
r DS ( ON
50 × 10 – 6
--------
N
(EQ. 19)
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
In certain circumstances, it may be necessary to adjust the
value of one or more of the ISEN resistors. This can arise
when the components of one or more channels are inhibited
from dissipating their heat so that the affected channels run
hotter than desired (see the section entitled Channel-Current
Balance ). In these cases, chose new, smaller values of R ISEN
for the affected phases. Choose R ISEN,2 in proportion to the
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase.
function, the gain of the current signal, and the value of the
compensation components, R C and C C .
Since the system poles and zero are effected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
R ISEN , 2 = R ISEN ---------- 2
? T
? T 1
(EQ. 20)
yields a solution that is always stable with very close to ideal
transient performance.
In Equation 20, make sure that ? T 2 is the desired temperature
rise above the ambient temperature, and ? T 1 is the measured
temperature rise above the ambient temperature. While a
C 2 (OPTIONAL)
single adjustment according to Equation 20 is usually
sufficient, it may occasionally be necessary to adjust R ISEN
R C
C C
COMP
two or more times to achieve perfect thermal balance between
all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R FB in Figure 5.
FB
Its value depends on the desired full-load droop voltage
(V DROOP in Figure 5). If Equation 19 is used to select each
ISEN resistor, the load-line regulation resistor is as shown
R FB
+
V DROOP
IOUT
in Equation 21.
-
– 6
V DROOP
R FB = -------------------------
50 × 10
(EQ. 21)
VDIFF
If one or more of the ISEN resistors was adjusted for thermal
balance, as in Equation 20, the load-line regulation resistor
V DROOP
R FB = --------------------------------
R ISEN ( n )
should be selected according to Equation 22. Where I FL is
the full-load operating current and R ISEN(n) is the ISEN
resistor connected to the n th ISEN pin.
(EQ. 22)
I FL r DS ( ON ) n
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
15
FIGURE 12. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6559 CIRCUIT
The feedback resistor, R FB , has already been chosen as
outlined in Load-Line Regulation Resistor . Select a target
bandwidth for the compensated system, f 0 . The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f 0
to the L-C pole frequency and the ESR zero frequency. For
FN9084.8
December 29, 2004
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