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| 型号： | ISL6559CR-T |
| 厂商： | Intersil |
| 文件页数： | 12/21页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 4MHz |
| 占空比： | 75% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6559
t DELAY = --------------------------------------------------- = 560 μ s
1.4 ( VID )
R FB 160 × 10 – 6
T SS
1 + -----------------------------------------
(EQ. 10)
outlines the interaction between the fault monitors and the
power good signal.
PGOOD
Following the delay, the soft start ramps linearly until V RAMP
reaches VID. For the system described above, this first linear
ramp will continue for approximately
UV
RAMP1 = ----------- – t DELAY
T SS
1.4
(EQ. 11
DAC
REFERENCE
+
350mV
-
POR
CIRCUIT
OC
-
+
90 μ A
I AVG
= 5.27ms
VDIFF
+
OV
OVP
-
The final portion of the soft-start sequence is the time
remaining after V RAMP reaches VID and before I RAMP gets to
zero. This is also characterized by a slight change in the slope
of the output voltage ramp which, for the current example,
exists for a time of
2.2V
FIGURE 10. POWER GOOD AND PROTECTION CIRCUITRY
t RAMP2 = T SS – t RAMP1 – t DELAY
(EQ. 12)
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
t DELAY t RAMP1
t RAMP2
= 2.34ms
This behavior is seen in the example in Figure 9 of a converter
switching at 500kHz. For this converter, R FB is set to 2.67k ?
leading to T SS = 4.0ms, t DELAY = 700ns, t RAMP1 = 2.23ms,
and t RAMP2 = 1.17ms.
VOUT, 500mV/DIV
EN, 5V/DIV
1ms/DIV
FIGURE 9. SOFT-START WAVEFORMS FOR ISL6559 BASED
MULTI-PHASE BUCK CONVERTER
NOTE: Switching frequency 500kHz and R FB = 2.67k ?
Fault Monitoring and Protection
The ISL6559 actively monitors voltage and current feedback
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indication signal is provided for linking
to external system monitors. The schematic in Figure 10
12
which indicates that the converter is operating properly and
the output voltage is within a set window. The under-voltage
(UV) and over-voltage (OV) comparators create the output
voltage window. The controller also takes advantage of
current feedback to detect output over-current (OC)
conditions. PGOOD pulls low during shutdown and releases
high during soft-start once the output voltage exceeds the
UV threshold. Once high, PGOOD will only transition low
when the controller is disabled or a fault condition is
detected. It will return high under certain circumstances
once a fault clears.
Under-Voltage Protection
The voltage on V DIFF is internally offset by 350mV before it
is compared with the DAC reference voltage. By positively
offsetting the output voltage, an UV threshold is created
which moves relative to the VID code. During soft-start, the
slow rising output voltage eventually exceeds the UV
threshold. Assuming the POR leg of the PGOOD NOR gate
has not detected an OC fault, the PGOOD signal will go
high.
If a fault condition arises during operation and the output
voltage drops below the UV threshold, PGOOD will
immediately pull low, but converter operation will continue.
PGOOD will return high once the output voltage surpasses
the UV threshold.
If the ISL6559 is disabled during operation, the PGOOD
signal will not pull low until the output voltage decays below
the UV threshold.
FN9084.8
December 29, 2004
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