参数资料
型号: ISL6561CRZ-T
厂商: Intersil
文件页数: 13/26页
文件大小: 0K
描述: IC CTLR PWM MULTIPHASE 40-QFN
标准包装: 1
应用: 控制器,Intel VR10X
输入电压: 3 V ~ 12 V
输出数: 4
输出电压: 0.84 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 标准包装
产品目录页面: 1243 (CN2011-ZH PDF)
其它名称: ISL6561CRZ-TDKR
ISL6561
INDUCTOR DCR Sensing
An inductor has a distributed direct current winding
resistance (DCR). Consider the inductor DCR as a separate
lumped quantity as shown in Figure 4. The channel current,
I L , flowing through the inductor, also passes through the
DCR. Equation 4 shows the s-domain equivalent voltage,
V L , across the inductor.
Current Sampling
During the forced off-time following a PWM transition low, the
associated channel current sense amplifier reproduces a
signal , I SEN , proportional to the inductor current, I L .
Regardless of the current sense method, I SEN is simply a
scaled version of the inductor current. Coincident with the
falling edge of the PWM signal, the sample and hold circuitry
V L = I L ? ( s ? L + DCR )
(EQ. 4)
samples I SEN . This is illustrated in Figure 5. The sample
time, t SAMP , is fixed and equal to 1/3 of the switching period,
t SW . Therefore, the sample current, I n , is proportional to the
t SAMP = ---------- = ------------------
3 ? f SW
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 5.
The voltage on the capacitor, V C , can be shown to be
t SW 1
3
(EQ. 7)
proportional to the channel current I L (see Equation 5).
output current and held for one switching cycle. The sample
? s ? ------------- + 1 ? ? ( DCR ? I )
V C = ---------------------------------------------------------------------
? DCR ? L
L
( s ? RC + 1 )
(EQ. 5)
current is used for current balance, load-line regulation, and
overcurrent protection.
If the R-C network components are selected such that the R-
C time constant matches the inductor L/DCR time constant,
then V C is equal to the voltage drop across the DCR.
I L
V IN
I L ( s )
PWM
L
DCR
V OUT
ISL6561
INDUCTOR
V L
C OUT
I SEN
V C (s)
PWM(n)
ISL6561 INTERNAL CIRCUIT
I n
SAMPLE
&
R
C
R ISEN
t SAMP
SAMPLE CURRENT, I n
SWITCHING PERIOD
TIME
FIGURE 5. SAMPLE AND HOLD TIMING
HOLD
ISEN-
Channel-Current Balance
I SEN = I -------------------
L R
+
-
ISEN+
DCR
ISEN
FIGURE 4. DCR SENSING CONFIGURATION
The capacitor voltage, V C , is replicated across the sense
resistor R ISEN . so that the current flowing through the sense
resistor is proportional to the inductor current. Equation 6
shows that the relationship between the channel current and
the sensed current I SEN , is driven by the value of the sense
resistor and the inductor DCR.
The sampled currents I n , from each active channel are
summed together and divided by the number of active
channels. The resulting cycle average current, I AVG ,
provides a measure of the total load current demand on the
converter during each switching cycle. Channel current
balance is achieved by comparing the sampled current of
each channel to the cycle average current, and making an
appropriate adjustment to each channel pulse width based
on the error. Intersil’s patented current-balance method is
illustrated in Figure 6, with error correction for channel 1
represented. In the figure, the cycle average current
combines with the channel 1 sample, I 1 , to create an error
signal I ER . The filtered error signal modifies the pulse width
commanded by V COMP to correct any unbalance and force
I SEN = I L ? ------------------
DCR
R ISEN
13
(EQ. 6)
I ER toward zero. The same method for error signal correction
is applied to each active channel.
FN9098.5
May 12, 2005
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