参数资料
型号: ISL6597CRZ-T
厂商: Intersil
文件页数: 5/10页
文件大小: 0K
描述: IC MOSFET DRVR DUAL SYNC 16-QFN
标准包装: 6,000
配置: 高端和低端,同步
输入类型: 非反相
延迟时间: 18ns
配置数: 2
输出数: 4
高端电压 - 最大(自引导启动): 36V
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-VQFN 裸露焊盘
供应商设备封装: 16-QFN-EP(4x4)
包装: 带卷 (TR)
ISL6597
Electrical Specifications
These specifications apply for T A = 0°C to +70°C, unless otherwise noted (Continued)
PARAMETER
LGATE Fall Time
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
SYMBOL
t FL
t PDLU
t PDLL
t PDHU
t PDHL
t PTS
TEST CONDITIONS
V VCC = 5V, 3nF Load
V VCC = 5V, Unloaded,
V VCC = 5V, Unloaded,
V VCC = 5V, Unloaded,
V VCC = 5V, Unloaded,
V VCC = 5V, Unloaded
MIN
-
-
-
-
-
-
TYP
4.0
18
25
18
23
30
MAX
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
OUTPUT (Note 3)
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
R UG_SRC
R UG_SNK
R LG_SRC
R LG_SNK
250mA Source Current
250mA Sink Current
250mA Source Current
250mA Sink Current
-
-
-
-
1.0
1.0
1.0
0.4
2.5
2.5
2.5
1.0
Ω
Ω
Ω
Ω
NOTE:
3. Guaranteed by Characterization. Not 100% tested in production.
Functional Pin Description
PACKAGE
PIN
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SYMBOL
GND
LGATE1
PVCC
EN
PGND
LGATE2
VCTRL
PHASE2
UGATE2
BOOT2
BOOT1
UGATE1
PHASE1
VCC
PWM1
PWM2
PAD
FUNCTION
Bias and reference ground. All signals are referenced to this node.
Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from
this pin to PGND.
Enable input pin. Connect this pin high to enable and low to disable the driver.
It is the power ground return of both low gate drivers.
Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
This pin sets the PWM logic threshold. Connect this pin to 3.3V source for 3.3V PWM input and pull it to 5V source for
5V PWM input.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin
provides a return path for the upper gate drive.
Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin
and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap
Considerations” on page 7 for guidance in choosing the capacitor value.
Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin
and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap
Considerations” on page 7 for guidance in choosing the capacitor value.
Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin
provides a return path for the upper gate drive.
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
capacitor from this pin to GND.
The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation,
see “Tri-State PWM Input” on page 6 for further details. Connect this pin to the PWM output of the controller.
The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation,
see “Tri-State PWM Input” on page 6 for further details. Connect this pin to the PWM output of the controller.
Connect this pad to the power ground plane (PGND) via thermally enhanced connection.
5
FN9165.1
May 4, 2007
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