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| 型号： | ISL6597CRZ |
| 厂商： | Intersil |
| 文件页数： | 7/10页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR DUAL SYNC 16-QFN |
| 标准包装： | 75 |
| 配置： | 高端和低端，同步 |
| 输入类型： | 非反相 |
| 延迟时间： | 18ns |
| 配置数： | 2 |
| 输出数： | 4 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN-EP（4x4） |
| 包装： | 管件 |
ISL6597
PWM line of ISL6597 (assuming an Intersil PWM controller
is used).
Bootstrap Considerations
This driver features an internal bootstrap diode. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
The following equation helps select a proper bootstrap
capacitor size:
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the 16 lead 4x4 QFN packages, with an exposed heat
escape pad, is around 2W. See Layout Considerations
paragraph for thermal transfer improvement suggestions.
When designing the driver into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses due to
C BOOT_CAP ≥ --------------------------------------
Q GATE
Δ V BOOT_CAP
(EQ. 1)
the gate charge of MOSFETs and the driver ’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively,
Q GATE = ------------------------------------ ? N Q1
P Qg_Q1 = --------------------------------------- ? F SW ? N Q1
P Qg_Q2 = --------------------------------------- ? F SW ? N Q2
? Q G1 ? N Q1 Q G2 ? N Q2 ?
I DR = 2 ? ? ? ? F SW + I Q
Q G1 ? PVCC
V GS1
where Q G1 is the amount of gate charge per upper MOSFET
at V GS1 gate-source voltage and N Q1 is the number of
control MOSFETs. The Δ V BOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
As an example, suppose two HAT2168 FETs are chosen as
the upper MOSFETs. The gate charge (Q G ) from the data
sheet is 12nC at 5V (V GS ) gate-source voltage. Then the
Q GATE is calculated to be 26.4nC at 5.5V PVCC level. We
will assume a 100mV droop in drive voltage over the PWM
P Qg_TOT = 2 ? ( P Qg_Q1 + P Qg_Q2 ) + I Q ? VCC
Q G1 ? PVCC 2
V GS1
Q G2 ? PVCC 2
V GS2
------------------------------ + ------------------------------
? V GS1 V GS2 ?
(EQ. 2)
(EQ. 3)
cycle. We find that a bootstrap capacitance of at least
0.264 μ F is required. The next larger standard value
capacitance is 0.33μF. A good quality ceramic capacitor is
recommended.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
where the gate charge (Q G1 and Q G2 ) is defined at a
particular gate to source voltage (V GS1 and V GS2 ) in the
corresponding MOSFET datasheet; I Q is the driver ’s total
quiescent current with no load at both drive outputs; N Q1
and N Q2 are number of upper and lower MOSFETs,
respectively. The factor 2 is the number of active channels.
The I Q V CC product is the quiescent power of the driver
without capacitive load and is typically negligible.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R G1 and R G2 , should be a short to avoid
0.6
0.4
Q GATE = 100nC
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R GI1 and R GI2 ) of
MOSFETs. Figures 3 and 4 show the typical upper and lower
0.2
20nC
50nC
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as:
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
Δ V BOOT (V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F SW ), the output drive impedance, the
P DR = 2 ? ( P DR_UP + P DR_LOW ) + I Q ? VCC
? R HI1 R LO1 ? P Qg_Q1
? R HI2 R LO2 ? P Qg_Q2
2
2
(EQ. 4)
R EXT2 = R G1 + -------------
N
R EXT2 = R G2 + -------------
N
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
7
R GI1
Q1
R GI2
Q2
FN9165.1
May 4, 2007
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| ISL6597CRZ-T | 功能描述:IC MOSFET DRVR DUAL SYNC 16-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:高端 输入类型:非反相 延迟时间:200ns 电流 - 峰:250mA 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:600V 电源电压:12 V ~ 20 V 工作温度:-40°C ~ 125°C 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-DIP 包装:管件 其它名称:*IR2127 |
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| ISL6605CB | 功能描述:IC MOSFET DRVR SYNC BUCK 8-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:低端 输入类型:非反相 延迟时间:40ns 电流 - 峰:9A 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:- 电源电压:4.5 V ~ 35 V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263 包装:管件 |
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