参数资料
型号: ISL6608IR-T
厂商: Intersil
文件页数: 9/11页
文件大小: 0K
描述: IC MOSFET DRVR SYNC BUCK 8-QFN
标准包装: 6,000
配置: 高端和低端,同步
输入类型: PWM
延迟时间: 20ns
电流 - 峰: 2A
配置数: 1
输出数: 2
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-VQFN 裸露焊盘
供应商设备封装: 8-QFN(3x3)
包装: 带卷 (TR)
ISL6608
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction tem perature of 125 ° C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommende d that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as below and plotted as in
Figure 9.
Layout Consideration
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
P = f sw ( 1.5V U Q U + V L Q L ) + I DDQ V
CC
in between power components is required for good airflow.
The gate traces from the drivers to the FETs should be kept
short and wide to reduce the inductance of the traces and
where f sw is the switching frequency of the PWM signal. V U
and V L represent the upper and lower gate rail voltage. Q U
and Q L are the upper and lower gate charge determined by
MOSFET s election and any external capacitance added to
the gate pins. The I DDQ V CC product is the quiescent power
of the driver and is typically negligible.
promote clean drive signals.
1000
900
Q U =100nC
Q L =200nC
Q U =50nC
Q L =100nC
Q U =50nC
Q L =50nC
800
700
600
500
400
300
200
100
Q U =20nC
Q L =50nC
0
0
200
400
600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 9. POWER DISSIPATION vs FREQUENCY
9
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