参数资料
型号: ISL6610ACRZ
厂商: Intersil
文件页数: 5/11页
文件大小: 0K
描述: IC MOSFET DRVR DUAL SYNC 16-QFN
标准包装: 75
配置: 高端和低端,同步
输入类型: PWM
延迟时间: 18ns
配置数: 2
输出数: 4
高端电压 - 最大(自引导启动): 36V
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-VQFN 裸露焊盘
供应商设备封装: 16-QFN-EP(4x4)
包装: 管件
ISL6610, ISL6610A
Electrical Specifications
These specifications apply for T A = -40°C to +85°C, unless otherwise noted (Continued)
PARAMETER
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
SYMBOL
t PDHU
t PDHL
t PTS
TEST CONDITIONS
Outputs Unloaded
Outputs Unloaded
Outputs Unloaded
MIN
-
-
-
TYP
18
23
20
MAX
-
-
-
UNITS
ns
ns
ns
OUTPUT (Note 4)
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
R UG_SRC
R UG_SNK
R LG_SRC
R LG_SNK
250mA Source Current
250mA Sink Current
250mA Source Current
250mA Sink Current
-
-
-
-
1.0
1.0
1.0
0.4
2.5
2.5
2.5
1.0
Ω
Ω
Ω
Ω
NOTE:
4. Guaranteed by Characterization. Not 100% tested in production.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
1
DFN
15
SYMBOL
PWM1
FUNCTION
The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
2
16
PWM2
The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
3
4
5
1
2
3
GND
LGATE1
PVCC
Bias and reference ground. All signals are referenced to this node.
Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor
from this pin to PGND.
6
-
7
8
4
5,8
6
7
PGND
NC1,2
LGATE2
PHASE2
Power ground return of both low gate drivers.
No connection.
Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This
pin provides a return path for the upper gate drive.
9
10
9
10
UGATE2
BOOT2
Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this
pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
11
11
BOOT1
Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this
pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
12
13
12
13
UGATE1
PHASE1
Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This
pin provides a return path for the upper gate drive.
14
14
VCC
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR
ceramic capacitor from this pin to GND.
-
17
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
FN6395.0
November 22, 2006
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