参数资料
| 型号： | ISL6627CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER VR11.1 VR12 10DFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VR11.1，VR12 |
| 输出数： | 1 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 带卷 (TR) |
ISL6627
P DR = P DR_UP + P DR_LOW + I Q ? VCC
Layout Considerations
A good layout helps reduce the ringing on the switching (PHASE)
P DR_UP = ? ? ? -------------------
? R HI1 R LO1 ? P Qg_Q1
? R HI1 + R EXT1
R LO1 + R EXT1 ?
2
P DR_LOW = ? ----------------------------------- + ------------------------------------- ? ? -------------------
R HI2 + R EXT2 R LO2 + R EXT2 ?
?
----------------------------------- + -------------------------------------
? R HI2 R LO2 ? P Qg_Q2
2
(EQ. 4)
node and significantly lower the stress applied to the MOSFETs as
well as the driver. The following advice is meant to lead to an
optimized layout:
? Keep decoupling circuit loops (VCC-GND and BOOT-PHASE) as
short as possible.
N N
R GI1 R GI2
R EXT1 = R G1 + ------------ R EXT2 = R G2 + ------------
Q1 Q2
The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the total
gate drive power losses, the rest will be dissipated by the external
gate resistors (R G1 and R G2 ) and the internal gate resistors (R GI1
and R GI2 ) of MOSFETs. Figures 5 and 6 show the typical upper and
lower gate drives turn-on current paths.
? Minimize trace inductance, especially on low-impedance lines.
All power traces (UGATE, PHASE, LGATE, GND, VCC) should be
short and wide, as much as possible.
? Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET should
be as close as thermally allowable.
? Minimize the current loop of the output and input power trains.
Short the source connection of the lower MOSFET to ground as
close to the transistor pin as feasible. Input capacitors
VCC
BOOT
C GD
D
(especially ceramic decoupling) should be placed as close to
the drain of upper and source of lower MOSFETs as possible.
In addition, connecting the thermal pad of the DFN package to
the power ground through one or several vias is recommended
R HI1
R LO1
G
R G1
R GI1
C GS
S
C DS
Q1
for high switching frequency, high current applications. This is to
improve heat dissipation and allow the part to achieve its full
thermal potential.
Upper MOSFET Self Turn-On Effects at Startup
PHASE
FIGURE 5. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
VCC
D
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high dV/dt
rate while the driver outputs are floating, due to self-coupling via
the internal C GD of the MOSFET, the gate of the upper MOSFET
could momentarily rise up to a level greater than the threshold
voltage of the device, potentially turning on the upper switch.
Therefore, if such a situation could conceivably be encountered,
R HI2
R LO2
G
R G2
C GD
R GI2
C GS
S
C DS
Q2
it is a common practice to place a resistor (R UGPH ) across the
gate and source of the upper MOSFET to suppress the Miller
coupling effect. The value of the resistor depends mainly on the
input voltage’s rate of rise, the C GD /C GS ratio, as well as the
gate-source threshold of the upper MOSFET. A higher dV/dt, a
lower C GD /C GS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of the
internal capacitive coupling. For most applications, the
integrated 20k Ω resistor is sufficient, not measurably affecting
FIGURE 6. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
MOSFET and Driver Selection
normal performance and efficiency.
The coupling effect can be roughly estimated with Equation 5,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components, such as lead
DS
? dV ?
dV
V GS_MILLER = ------ ? R ? C rss ? 1 – e dt
iss ?
The parasitic inductances of the PCB and of the power devices’
packaging (both upper and lower MOSFETs) can cause serious
ringing, exceeding absolute maximum rating of the devices. The
negative ringing at the edges of the PHASE node could increase
the bootstrap capacitor voltage through the internal bootstrap
diode, and in some cases, it may overstress the upper MOSFET
driver. Careful layout, proper selection of MOSFETs and
packaging, as well as the driver can minimize such unwanted
inductances and PCB capacitances are also not taken into
account. Figure 7 provides a visual reference for this
phenomenon and its potential solution.
– V
? ------------------------------- ?
------ ? R ? C
dt ? ?
? ?
? ?
(EQ. 5)
stress.
8
R = R UGPH + R GI
C rss = C GD
C iss = C GD + C GS
FN6992.1
January 24, 2014
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