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| 型号： | ISL6721AARZ-T |
| 厂商： | Intersil |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK ISO 16QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 9 V ~ 18 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6721A
A block diagram of the feedback control loop is shown in
Figure 7.
PRIMARY SIDE AMPLIFIER
signal in the control IC must be taken into account. The
maximum peak primary current was determined earlier to be
1.87A, so a choice of 2.25A peak primary current for current
limit is reasonable. A current gain, A EXT , of 0.5V/A was
Z3
REF +
-
PWM
POWER
STAGE
VOUT
selected to achieve this (Equation 26).
ISET = 2.25 ? 0.8 ? 0.5 + 0.100 = 1.00
V
(EQ. 26)
Z4
ERROR AMPLIFIER
The control to output transfer function may be represented as
shown in Equation 27:
1 + ------
v o R o ? L s ? f sw ω z
v c
1 + -------
ISOLATION
Z2
-
Z1
s
------ = K ? --------------------------------- ? -----------------
2 s
ω p
(EQ. 27)
+
REF
If we ignore the current feedback sampled-data effects
(Equations 28 through 35):
I spk ( max )
FIGURE 7. FEEDBACK CONTROL LOOP
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. The primary
side amplifier located in the control IC is used as a unity gain
inverting amplifier and provides no loop compensation. A
Type 2 error amplifier configuration was selected as a
K = --------------------------
V c ( max )
R o = LoadResis tan ce
L s = SecondaryInduc tan ce
(EQ. 28)
(EQ. 29)
(EQ. 30)
ω p = --------------------
f p = -----------------------------
ω z = --------------------
f z = --------------------------------------
precaution in case operation in continuous mode should
occur at some operating point (Figure 8).
V OUT
2
R o ? C o
1
R c ? C o
or
or
1
π ? R o ? C o
1
2 ? π ? R c ? C o
(EQ. 31)
(EQ. 32)
-
C o = OutputCapaci tan ce
(EQ. 33)
V ERROR
+
REF
R c = OutputCapaci tan ceE SR
(EQ. 34)
V c ( max ) = ControlVoltageRange
(EQ. 35)
FIGURE 8. TYPE 2 ERROR AMPLIFIER
Development of a small signal model for current mode
control is rather complex. The method of reference 1 was
selected for its ability to accurately predict loop behavior. To
The value of K may be determined by assuming all of the
output power is delivered by the 3.3V output at the threshold
of current limit. The maximum power allowed was
determined earlier as 15W, therefore (Equations 36, 37):
2 ? ------------ ? t sw
P out
2 ? -------- ? 5 × 10
I spk ( max ) = ------------------------------------ = ------------------------------------------ = 19.5
2.33 × 10
v c ( max ) = V ISENSE ? A EXT ? A CS ? --------------------- = 2.93
A
further simplify the analysis, the converter will be modeled as
a single output supply with all of the output capacitance
reflected to the 3.3V output. Once the “single” output system
is compensated, adjustments to the compensation will be
required based on actual loop measurements.
The first parameter to determine is the peak current
feedback loop gain. Since this application is low power, a
V out 3.3
Tr
15 – 6
1
COMP
A
(EQ. 36)
V
(EQ. 37)
resistor in series with the source of the power switching
MOSFET is used for the current feedback signal. For higher
power applications, a resistor would dissipate too much
power and current transformer would be used instead.
There is limited flexibility to adjust the current loop behavior
due to the need to provide overcurrent protection. Current
limit and the current loop gain are determined by the current
sense resistor and the ISET threshold. ISET was set at 1.0V,
near its maximum, to minimize noise effects. When
determining ISET, the internal gain and offset of the ISENSE
17
where A EXT is the external gain of the current feedback
network, A CS is the IC internal gain, and A COMP is the gain
between the error amplifier and the PWM comparator.
The Type 2 compensation configuration has two poles and
one zero. The first pole is at the origin, and provides the
integration characteristic which results in excellent DC
regulation. Referring to the Typical Application Schematic on
FN6797.0
August 23, 2011
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6721AAVZ | 功能描述:IC REG CTRLR PWM CM 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6721AAVZ-T | 功能描述:IC REG CTRLR PWM CM 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6721AB | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL6721AB-T | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL6721ABZ | 功能描述:电流型 PWM 控制器 FLEX SNG ENDED CUR MODE PWM CONTRLR RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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