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参数资料
| 型号： | ISL6722AARZ-T |
| 厂商： | Intersil |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK ISO 16QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 9 V ~ 18 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6722A, ISL6723A
For simplicity, only the final design is further described.
The peak and RMS current values in the remaining windings
2 ? Iout ? t sw
An EPCOS EFD 20/10/7 core using N87 material gapped to
an A L value of 25 nH/N 2 was chosen. It has more than the
required air gap volume to store the energy required, but
was needed for the window area it provides.
may be calculated in Equation 28:
Ispk = ---------------------------------- A
Tr
(EQ. 28)
t sw
Irms = 2 ? Iout ? ---------------
Aeff = 31 ? 10 -6
m 2
3 ? Tr
A
(EQ. 29)
lg = 1.56 ? 10 -3
m
The RMS current for the primary winding is 0.72A, for the
The flux density Δ B is only 0.069T or 690 gauss, a relatively
low value.
3.3V output, 4.23A, for the 1.8V output, 1.69A, and for the
bias winding, 85mA.
μ o ? N p ? Aeff
L p = ----------------------------------------
2
lg
μ H
(EQ. 25)
To minimize the transformer leakage inductance, the primary
was split into two sections connected in parallel and
positioned such that the other windings were sandwiched
Since the number of primary turns, N p , may be calculated.
The result is N p = 40 turns. The secondary turns may be
calculated in Equation 26:
between them. The output windings were configured so that
the 1.8V winding is a tap off of the 3.3V winding. Tapping the
1.8V output requires that the shared portion of the
N s ≤ ---------------------------------------------------------
Ig ? ? Vout + Vd ? ? Tr
N p ? Ippk ? μ o ? Aeff
(EQ. 26)
secondary conduct the combined current of both outputs.
The secondary wire gauge must be selected accordingly.
where Tr is the time required to reset the core. Since
discontinuous MMF mode operation is desired, the core
must completely reset during the off time. To maintain
discontinuous mode operation, the maximum time allowed to
reset the core is t sw - t ON(max) where t sw = 1/f sw . The
minimum time is application dependent and at the designers
discretion knowing that the secondary winding RMS current
and ripple current stress in the output capacitors increases
with decreasing reset time. The calculation for maximum N s
for the 3.3V output using T = t sw - t ON (max) = 2.75μs is 5.52
turns.
The determination of the number of secondary turns is also
dependent on the number of outputs and the required turns
ratios required to generate them. If schottky output rectifiers
are used and we assume a forward voltage drop of 0.45V,
the required turns ratio for the two output voltages, 3.3V and
1.8V, is 5:3.
With a turns ratio of 5:3 for the secondary windings, we will
use N s1 = 5 turns and N s2 = 3 turns. Checking the reset time
using these values for the number of secondary turns yields
a duration of Tr = 2.33μs or about 47% of the switching
period, an acceptable result.
The bias winding turns may be calculated similarly, only a
diode forward drop of 0.7V is used. The rounded off result is
17 turns for a 12V bias.
The next step is to determine the wire gauge. The RMS
current in the primary winding may be calculated in
Equation 27:
The determination of current carrying capacity of wire is a
compromise between performance, size, and cost. It is
affected by many design constraints such as operating
frequency (harmonic content of the waveform) and the
winding proximity/geometry. It generally ranges between
250 and 1000 circular mils per ampere. A circular mil is
defined as the area of a circle 0.001” (1 mil) in diameter. As
the frequency of operation increases, the AC resistance of
the wire increases due to skin and proximity effects. Using
heavier gauge wire may not alleviate the problem. Instead
multiple strands of wire in parallel must be used. In some
cases Litz wire is required.
The winding configuration selected is:
Primary #1: 40T, 2 #30 bifilar
Secondary: 5T, 0.003” (3 mil) copper foil tapped at 3T
Bias: 17T #32
Primary #2: 40T, 2 #30 bifilar
The internal spacing and insulation system was designed for
1500 VDC dielectric withstand rating between the primary
and secondary windings.
Power MOSFET Selection
Selection of the main switching MOSFET requires
consideration of the voltage and current stresses that will be
encountered in the application, the power dissipated by the
device, its size, and its cost.
The input voltage range of the converter is 36VDC to
Ip ( rms ) = Ippk ? ------------------------- )
t ON ( max
3 ? t sw
15
A
(EQ. 27)
75VDC. This suggests a MOSFET with a voltage rating of
150V is required due to the flyback voltage likely to be seen
on the primary of the isolation transformer.
FN9237.1
July 11, 2007
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