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| 型号： | ISL6722AAVZ |
| 厂商： | Intersil |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM CM 16-TSSOP |
| 标准包装： | 960 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 9 V ~ 18 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
ISL6722A, ISL6723A
The minimum amount of slope compensation required
corresponds to 1/2 the inductor downslope. However, adding
be shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is Equation 9:
Fm = ---------------------
excessive slope compensation results in a control loop that
behaves more as a voltage mode controller than as current
mode controller.
1
Sn ? t sw
(EQ. 9)
Fm = ------------------------------------ = -------------------------
Sense Signal Current
CURRENT SENSE SIGNAL
Downslope
DOWNSLOPE
where Sn is the slope of the sawtooth signal and t sw is the
switching frequency. When an external ramp is added, the
modulator gain becomes Equation 10:
1 1
(EQ. 10)
( Sn + Se ) t sw m c Snt sw
where Se is slope of the external ramp.
m c = 1 + -------
Time
TIME
FIGURE 5.
Se
Sn
(EQ. 11)
The minimum amount of capacitance to place at the SLOPE
pin is:
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
Cslope = 4.24 × 10
t ON
– 6
? --------------------
Vslope
F
(EQ. 6)
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, under-damped for Q > 1,
and over-damped for Q < 1. An under-damped condition
where t ON is the On time and Vslope is the amount of
may result in current loop instability.
Q = -------------------------------------------------
voltage to be added as slope compensation to the current
feedback signal. In general, the amount of slope
compensation added is 2 to 3 times the minimum required.
1
π ( m c ( 1 – D ) – 0.5 )
(EQ. 12)
Example:
Assume the inductor current signal presented at the ISENSE
where D is the maximum duty cycle. Setting Q = 1 and
solving for S e yields:
S e = S n ? ? --- + 0.5 ? ------------- – 1 ?
pin decreases 125mV during the Off period, and:
Switching Frequency, f sw = 250kHz
1 1
? ? π ? 1 – D ?
(EQ. 13)
Duty Cycle, D = 60%
t ON = D/f sw = 0.6/250E3 = 2.4μs
Since S n and S e are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by t ON to obtain the voltage change that occurs during t ON .
V e = V n ? ? --- + 0.5 ? ------------- – 1 ?
t OFF = (1 - D)/f sw = 1.6μs
Determine the downslope:
1 1
? ? π ? 1 – D ?
(EQ. 14)
Vslope = --- ? 0.078 ? 2.4 = 94mV
Downslope = 0.125V/1.6μs = 78mV/μs. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time.
1
(EQ. 7)
2
Therefore,
where V n is the change in the current feedback signal during
the on time and V e is the voltage that must be added by the
external ramp.
For buck-derived topologies, V n can be solved for in terms of
output voltage, current transducer components, and output
inductance yielding:
Cslope ( min ) = 4.24 × 10
2.4 × 10
V e = ---------------------------------------- ? -------- ? --- + D – 0.5 ?
N P ? π
N CT ? L O
– 6
– 6
? ----------------------- ≈ 110pF
0.094
(EQ. 8)
t SW ? V O ? R CS N S 1
?
V
(EQ. 15)
The value calculated, 110pF, represents the minimum slope
compensation required. An appropriate slope compensation
capacitance for this example would be 1/2 to 1/3 the
calculated value, or between 68pF and 33pF.
A more rigorous treatment of slope compensation can be
obtained from the small signal current-mode model [1]. It can
11
where R CS is the current sense burden resistor, N CT is the
current transformer turns ratio, L O is the output inductance,
V O is the output voltage, and N s and N p are the secondary
and primary turns, respectively.
FN9237.1
July 11, 2007
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| ISL6722AAVZ-T | 功能描述:IC REG CTRLR PWM CM 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6723AABZ | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6723AABZ-T | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6726AAZ | 功能描述:IC REG CTRLR ISO PWM CM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
| ISL6726AAZ-T | 功能描述:IC REG CTRLR ISO PWM CM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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