参数资料
型号: ISL6740IBZ-T
厂商: Intersil
文件页数: 16/28页
文件大小: 0K
描述: IC REG CTRLR PWM VM 16-SOIC
标准包装: 2,500
PWM 型: 电压模式
输出数: 2
频率 - 最大: 2MHz
占空比: 100%
电源电压: 9 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 105°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
ISL6740, ISL6741
square mils yields 555mils 2 (0.785 sq. mils/c.m.). Dividing by
the trace width results in a copper thickness of 4.44 mils
between the two secondary windings. The winding layout
appears below.
(0.112mm). Using 1.3 mils/oz. of copper requires a copper
weight of 3.4oz. For reasons of cost, 3oz. copper was selected.
One layer of each secondary winding also contains the
synchronous rectifier winding. For this layer the secondary trace
width is reduced by 0.025 inches to 0.100 inches(0.015 inches
for the SR winding trace width and 0.010 inches spacing
between the SR winding and the secondary winding).
The choice of copper weight may be validated by calculating the
DC copper losses of the secondary winding as follows. Ignoring
the terminal and lead-in resistance, the resistance of each layer
of the secondary may be approximated using Equation 18.
FIGURE 7A. TOP LAYER: 1 TURN SECONDARY AND SR
2 πρ
? r 2 ?
? r 1 ?
R = ------------------------
t ? ln ? ----- ?
Ω
(EQ. 18)
WINDINGS
where
R = Winding resistance
ρ = Resistivity of copper = 669e-9 Ω -inches at 20°C
t = Thickness of the copper (3 oz.) = 3.9e-3 inches
r 2 = Outside radius of the copper trace = 0.324 or 0.299 inches
r 1 = Inside radius of the copper trace = 0.199 inches
The winding without the SR winding on the same layer has a DC
resistance 2.21m Ω . The winding that shares the layer with the
SR winding has a DC resistance of 2.65m Ω . With the secondary
configured as a 4 turn center tapped winding (2 turns each side
of the tap), the total DC power loss for the secondary at +20°C is
486mW.
The primary windings have an RMS current of approximately 5A
(I OUT x N S /N P at ~ 100% duty cycle). The primary is configured as
2 layers, 2 turns per layer to minimize the winding stack height.
Allowing 0.020 inches edge clearance and 0.010 inches between
turns yields a trace width of 0.0575 inches. Ignoring the terminal
and lead-in resistance, and using Equation 18, the inner trace
has a resistance of 4.25m Ω , and the outer trace has a resistance
of 5.52m Ω . The resistance of the primary then is 19.5m Ω at
+20°C. The total DC power loss for the secondary at +20°C is
489mW.
Improved efficiency and thermal performance could be achieved
FIGURE 7B. INT. LAYER 1: 1 TURN SECONDARY WINDING
FIGURE 7C. INT. LAYER 2: 2 TURNS PRIMARY WINDING
by selecting heavier copper weight for the windings. Evaluation in
the application will determine its need.
The order and geometry of the windings affects the AC
resistance, winding capacitance, and leakage inductance of the
finished transformer. To mitigate these effects, interleaving the
windings is necessary. The primary winding is sandwiched
FIGURE 7D. INT. LAYER 3: 2 TURNS PRIMARY WINDING
16
FN9111.6
December 2, 2011
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ISL6740IVZ-T 功能描述:IC REG CTRLR PWM VM 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
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