- 您现在的位置：买卖IC网 > PDF目录17287 > ISL6752/54EVAL1Z (Intersil)BOARD DEMO FOR ISL6752 ISL6754 PDF资料下载
参数资料
| 型号： | ISL6752/54EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR ISL6752 ISL6754 |
| 标准包装： | 1 |
| 主要目的： | 电源，ATX |
| 输出及类型： | 1，隔离 |
| 输出电压： | 12V |
| 电流 - 输出： | 50A |
| 输入电压： | 350 ~ 450 V |
| 稳压器拓扑结构： | 全桥式 |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL6752，ISL6754 |
ISL6752
capacitance. Each switch is designated by its position; upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 10, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
are indicated by I P and I S , respectively.
VIN+
During the period when CT discharges (also referred to as
the deadtime), the upper switches toggle. Switch UL turns off
and switch UR turns on. The actual timing of the upper
switch toggle is dependent on RESDEL, which sets the
resonant delay. The voltage applied to RESDEL determines
how far in advance the toggle occurs prior to a lower switch
turning on. The ZVS transition occurs after the upper
UL
UR
L L
D1
I S
VOUT+
switches toggle and before the diagonal lower switch turns
on. The required resonant delay is 1/4 of the period of the LC
I P
resonant frequency of the circuit formed by the leakage
τ = --- -----------------------------------
2
--------------- – ----------
L L C P
VIN-
LL
LR
D2
RTN
inductance and the parasitic capacitance. The resonant
transition may be estimated from Equation 25.
π 1
(EQ. 25)
2
1 R
2
4L L
FIGURE 10. UL - LR POWER TRANSFER CYCLE
The UL - LR power transfer period terminates when switch
LR turns off as determined by the PWM. The current flowing
in the primary cannot be interrupted instantaneously, so it
must find an alternate path. The current flows into the
parasitic switch capacitance of LR and UR, which charges
where τ is the resonant transition time, L L is the leakage
inductance, C P is the parasitic capacitance, and R is the
equivalent resistance in series with L L and C P .
The resonant delay is always less than or equal to the
deadtime and may be calculated using Equation 26.
τ resdel = -------------------- ? DT
the node to VIN and then forward biases the body diode of
upper switch UR.
V resdel
2
S
(EQ. 26)
VIN+
UL
UR
D1
I S
where τ resdel is the desired resonant delay, V resdel is a
L L
VOUT+
voltage between 0V and 2V applied to the RESDEL pin, and
I P
RTN
DT is the deadtime (see Equations 1 through 5).
When the upper switches toggle, the primary current that was
LL
LR
flowing through UL must find an alternate path. It
D2
VIN-
FIGURE 11. UL - UR FREE-WHEELING PERIOD
The primary leakage inductance, L L , maintains the current,
charges/discharges the parasitic capacitance of switches UL
and LL until the body diode of LL is forward-biased. If
RESDEL is set properly, switch LL will be turned on at this
time. The output inductor does not assist this transition. It is
purely a resonant transition driven by the leakage inductance.
which now circulates around the path of switch UL, the
transformer primary, and switch UR. When switch LR opens,
the output inductor current free-wheels through both output
diodes, D1 and D2. During the switch transition, the output
VIN+
UL
UR
L L
D1
I S
VOUT+
inductor current assists the leakage inductance in charging
the upper and lower bridge FET capacitance.
The current flow from the previous power transfer cycle
LL
I P
LR
D2
RTN
tends to be maintained during the free-wheeling period
because the transformer primary winding is essentially
shorted. Diode D1 may conduct very little or none of the
free-wheeling current, depending on circuit parasitics. This
behavior is quite different than occurs in a conventional
hard-switched full-bridge topology where the free-wheeling
current splits nearly evenly between the output diodes, and
flows not at all in the primary.
This condition persists through the remainder of the half
cycle.
13
VIN-
FIGURE 12. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
FN9181.3
October 31, 2008
相关PDF资料 |
PDF描述 |
|---|---|
| HMM02DSAN | CONN EDGECARD 4POS R/A .156 SLD |
| NSF8MT-E3/45 | DIODE 8A 1000V GPP PLAST TO220-2 |
| ASPI-0403S-470M-T | INDUCTOR POWER 47UH 20% SMD |
| NUD3112DMT1 | IC INDCT LOAD/RELAY DRVR SC74-6 |
| GMM06DTKS | CONN EDGECARD 12POS DIP .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6752AAZA | 功能描述:IC REG CTRLR PWM CM 16-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
| ISL6752AAZAR5325 | 制造商:Intersil Corporation 功能描述:- Rail/Tube |
| ISL6752AAZA-T | 功能描述:IC REG CTRLR PWM CM 16-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6752AAZA-TR5325 | 制造商:Intersil Corporation 功能描述:ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control |
| ISL6752DBEVAL1Z | 功能描述:BOARD DEMO FOR ISL6752 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:* 标准包装:1 系列:- 主要目的:DC/DC，步降 输出及类型:1，非隔离 功率 - 输出:- 输出电压:3.3V 电流 - 输出:3A 输入电压:4.5 V ~ 28 V 稳压器拓扑结构:降压 频率 - 开关:250kHz 板类型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名称:497-12113STEVAL-ISA094V1-ND |
发布紧急采购，3分钟左右您将得到回复。