参数资料
| 型号： | ISL78210ARUZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/17页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI-OUTPUT 32TQFP |
| 标准包装： | 3,000 |
| 应用： | 电源，汽车应用 |
| 输入电压： | 3.3 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 3.3 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFQFN |
| 供应商设备封装： | 16-UTQFN（2.6x1.8） |
| 包装： | 带卷 (TR) |
ISL78210
given by Equation 6:
Although the converter has latched-off in response to an OVP fault,
V ROCSET = 10 μ A ? R OCSET
(EQ. 6)
the LGATE gate-driver output will retain the ability to toggle the
low-side MOSFET on and off, in response to the output voltage
I OC ? DCR
R OCSET = ----------------------------
(EQ. 9)
C SEN = ------------------------------------------
The DC voltage difference between the OCSET pin and the VO pin,
which is given by Equation 7:
V OCSET – V VO = V DCR – V ROCSET = I L ? DCR – I OCSET ? R OCSET
(EQ. 7)
The IC monitors the voltage of the OCSET pin and the VO pin.
When the voltage of the OCSET pin is higher than the voltage of
the VO pin for more than 10μs, an OCP fault latches the
converter off.
Component Selection For R OCSET and C SEN
The value of R OCSET is calculated with Equation 8 which is
written as follows:
(EQ. 8)
I OCSET
Where:
- R OCSET ( Ω ) is the resistor used to program the overcurrent
setpoint
- I OC is the output DC load current that will activate the OCP
fault detection circuit
- DCR is the inductor DC resistance
For example, if I OC is 20A and DCR is 4.5m ? , the choice of
R OCSET is = 20Ax4.5m ? /10μA = 9k ? .
Resistor R OCSET and capacitor C SEN form an R-C network to
sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant R OCSET C SEN needs to
match the inductor time constant L/DCR. The value of C SEN is
then written as follows:
L
R OCSET ? DCR
For example, if L is 1.5μH, DCR is 4.5m ? , and R OCSET is 9k ? , the
choice of C SEN = 1.5μH/(9k ? x4.5m ? ) = 0.037μF.
When an OCP fault is declared, the PGOOD pin will pull-down to
35 Ω and latch off the converter. The fault will remain latched
until the EN pin has been pulled below the falling EN threshold
voltage V ENTHF or if VCC has decayed below the falling POR
threshold voltage V VCC_THF
Overvoltage
The OVP fault detection circuit triggers after the FB pin voltage is
above the rising overvoltage threshold V OVRTH for more than 2μs.
For example, if the converter is programmed to regulate 1.0V at
the FB pin, that voltage would have to rise above the typical
V OVRTH threshold of 116% for more than 2μs in order to trip the
OVP fault latch. In numerical terms, that would be
116% x 1.0V = 1.16V. When an OVP fault is declared, the PGOOD
pin will pull-down to 65 ? and latch-off the converter. The OVP
fault will remain latched until VCC has decayed below the falling
POR threshold voltage VVCC_THF . An OVP fault cannot be reset by
pulling the EN pin below the falling EN threshold voltage V ENTHF .
8
transversing the V OVRTH and V OVFTH thresholds. The LGATE
gate-driver will turn-on the low-side MOSFET to discharge the
output voltage, protecting the load. The LGATE gate-driver will
turn-off the low-side MOSFET once the FB pin voltage is lower than
the falling overvoltage threshold V OVRTH for more than 2μs. The
falling overvoltage threshold V OVFTH is typically 102%. That means
if the FB pin voltage falls below 102% x 1.0V = 1.02V, for more
than 2μs, the LGATE gate-driver will turn off the low-side MOSFET.
If the output voltage rises again, the LGATE driver will again turn on
the low-side MOSFET when the FB pin voltage is above the rising
overvoltage threshold V OVRTH for more than 2μs. By doing so, the
IC protects the load when there is a consistent overvoltage
condition.
Undervoltage
The UVP fault detection circuit triggers after the FB pin voltage is
below the undervoltage threshold V UVTH for more than 2μs. For
example, if the converter is programmed to regulate 1.0V at the
FB pin, that voltage would have to fall below the typical V UVTH
threshold of 84% for more than 2μs in order to trip the UVP fault
latch. In numerical terms, that would be 84% x 1.0V = 0.84V. When
a UVP fault is declared, the PGOOD pin will pull-down to 95 ? and
latch-off the converter. The fault will remain latched until the EN
pin has been pulled below the falling EN threshold voltage
V ENTHF or if VCC has decayed below the falling POR threshold
voltage V VCC_THF .
Over-Temperature
When the temperature of the IC increases above the rising
threshold temperature T OTRTH , it will enter the OTP state that
suspends the PWM, forcing the LGATE and UGATE gate-driver
outputs low. The status of the PGOOD pin does not change nor
does the converter latch-off. The PWM remains suspended until
the IC temperature falls below the hysteresis temperature
T OTHYS , at which time normal PWM operation resumes. The OTP
state can be reset if the EN pin is pulled below the falling EN
threshold voltage V ENTHF or if VCC has decayed below the falling
POR threshold voltage VVCC_THF . All other protection circuits
remain functional while the IC is in the OTP state. It is likely that
the IC will detect an UVP fault because in the absence of PWM,
the output voltage decays below the undervoltage threshold
V UVTH .
Theory of Operation
The modulator features Intersil’s R 3 Robust-Ripple Regulator
technology, a hybrid of fixed frequency PWM control and variable
frequency hysteretic control. The PWM frequency is maintained
at 300kHz under static continuous conduction mode operation
within the entire specified envelope of input voltage, output
voltage, and output load. If the application should experience a
rising load transient and/or a falling line transient such that the
output voltage starts to fall, the modulator will extend the on-
time and/or reduce the off-time of the PWM pulse in progress.
Conversely, if the application should experience a falling load
transient and/or a rising line transient such that the output
voltage starts to rise, the modulator will truncate the on-time
and/or extend the off-time of the PWM pulse in progress. The
FN7583.1
December 4, 2013
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