参数资料
| 型号： | ISL78215AUZ |
| 厂商： | Intersil |
| 文件页数： | 2/11页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK ISO 8MSOP |
| 标准包装： | 980 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 48% |
| 电源电压： | 7.5 V ~ 18 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 包装： | 管件 |
ISL78215
Pin Description
t D ≈ – RT ? CT ? ln ? ---------------------------------------------- ?
PIN
1
2
3
4
SYMBOL
COMP
FB
CS
RTCT
DESCRIPTION
COMP is the output of the error amplifier and the input of the PWM comparator. The control loop
frequency compensation network is connected between the COMP and FB pins.
The output voltage feedback is connected to the inverting input of the error amplifier through this pin.
The non-inverting input of the error amplifier is internally tied to a reference voltage.
This is the current sense input to the PWM comparator. The range of the input signal is nominally 0V to
1.0V and has an internal offset of 100mV.
This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by
connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to GND. The
oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The
charge time, tC, the discharge time, tD, the switching frequency, f, and the maximum duty cycle, Dmax,
can be calculated from Equations 1, 2, 3 and 4:
t C ≈ 0.583 ? RT ? CT
(EQ. 1)
0.0083 ? RT – 4.3
(EQ. 2)
? 0.0083 ? RT – 2.4 ?
f = 1 ? ( tC + tD )
(EQ. 3)
D = t
C
? f
(EQ. 4)
Figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given
frequency .
5
6
7
8
GND
OUT
VDD
VREF
GND is the power and small signal reference ground for all functions.
This is the drive output to the power switching device. It is a high current output capable of driving the
gate of a power MOSFET with peak currents of 1.0A.
VDD is the power connection for the device. The total supply current will depend on the load applied to
OUT. Total IDD current is the sum of the operating current and the average output current. Knowing the
operating frequency, f, and the MOSFET gate charge, Qg, the average output current can be calculated in
Equation 5:
I OUT = Qg × f
(EQ. 5)
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins
as possible .
The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature.
Bypass to GND with a 0.1μF to 3.3μF capacitor to filter this output as needed.
Ordering Information
PART NUMBER
TEMP RANGE
PACKAGE
PKG.
(Notes 2, 3)
ISL78215AUZ
ISL78215AUZ-T (Note 1)
PART MARKING
78215
78215
(°C)
-40 to +105
-40 to +105
(Pb-free)
8 Ld MSOP
8 Ld MSOP
M8.118
M8.118
DWG. #
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78215 . For more information on MSL please see techbrief TB363 .
2
FN7673.1
December 7, 2013
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