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| 型号： | ISL80101IR33Z-T |
| 厂商： | Intersil |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.3V 1A 10DFN |
| 标准包装： | 6,000 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.3V |
| 输入电压： | 最高 6V |
| 电压 - 压降（标准）： | 0.13V @ 1A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 1A（最小值） |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
ISL80101
Typical Operating Performance
Unless otherwise noted: V IN = 2.2V, V OUT = 1.8V, C IN = C OUT = 10μF, T J = +25°C, I L = 0A. (Continued)
10
V IN = 3.8V
V IN = 2.25V
V IN = 2V/DIV
V OUT = 5mV/DIV
1
0.1
0.01
I L = 1A
TIME (200μs/DIV)
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 14. LINE TRANSIENT RESPONSE
Applications Information
FIGURE 15. OUTPUT NOISE SPECTRAL DENSITY
C SS and the feedback reference voltage is clamped to the
voltage across it. The start-up time is set by Equation 1.
Input Voltage Requirements
The ISL80101 is capable of delivering the following fixed output
2 μ A
C SS x0.5
t start = ----------------------
(EQ. 1)
V OUT xC OUT x2 μ A
C SS = ---------------------------------------------
voltages: 1.8V, 2.5V, 3.3V, 5.0V. Due to the nature of an LDO, V IN
must be some margin higher than V OUT plus dropout at the
maximum rated current of the application if active filtering
(PSRR) is expected from V IN to V OUT . The generous dropout
specification of this family of LDOs allows applications to design
a level of efficiency.
Enable Operation
The ENABLE turn-on threshold is typically 800mV with 80mV of
hysteresis. An internal pull-up or pull-down resistor to change
these values is available upon request. As a result, this pin must
not be left floating, and should be tied to V IN if not used. A 1k Ω to
10k Ω pull-up resistor is required for applications that use open
collector or open drain outputs to control the ENABLE pin. The
ENABLE pin may be connected directly to V IN for applications
with outputs that are always on.
Power-Good Operation
PG is a logic output that indicates the status of V OUT and V IN . The
PG flag is an open-drain NMOS that can sink up to 10mA during a
fault condition. The PG pin requires an external pull-up resistor
typically connected to the V OUT pin. The PG pin should not be
pulled up to a voltage source greater than V IN . PG goes low when
the output voltage drops below 84% of the nominal output voltage or
if the part is disabled. PG functions during current limit and thermal
shutdown. For applications not using this feature, connect this pin to
ground.
Soft-Start Operation
The soft-start circuit controls the rate at which the output voltage
rises up to regulation at power-up or LDO enable. This start-up
ramp time can be set by adding an external capacitor from the
SS pin to ground. An internal 2μA current source charges up this
8
Equation 2 determines the C SS required for a specific start-up
in-rush current, where V OUT is the output voltage, C OUT is the
total capacitance on the output and I INRUSH is the desired in-rush
current.
(EQ. 2)
I INRUSH x0.5V
The external capacitor is always discharged to ground at the
beginning of start-up or enabling.
External Capacitor Requirements
External capacitors are required for proper operation. Careful
attention must be paid to the layout guidelines and selection of
capacitor type and value to ensure optimal performance.
OUTPUT CAPACITOR
The ISL80101 applies state-of-the-art internal compensation to
keep the selection of the output capacitor simple for the
customer. Stable operation over full temperature, V IN range,
V OUT range and load extremes are guaranteed for all capacitor
types and values assuming a minimum of 10μF X5R/X7R is used
for local bypass on V OUT . This output capacitor must be
connected to the V OUT and GND pins of the LDO with PCB traces
no longer than 0.5cm.
There is a growing trend to use very-low ESR multilayer ceramic
capacitors (MLCC) because they can support fast load transients
and also bypass very high frequency noise from other sources.
However, the effective capacitance of MLCCs drops with applied
voltage, age, and temperature. X7R and X5R dieletric ceramic
capacitors are strongly recommended as they typically maintain
a capacitance range within ±20% of nominal voltage over full
operating ratings of temperature and voltage.
FN6931.1
August 31, 2011
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| ISL80101IR33Z-TK | 功能描述:IC REG LDO 3.3V 1A 10DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:3,000 系列:- 稳压器拓扑结构:正，可调式 输出电压:1.2 V ~ 5.5 V 输入电压:1.7 V ~ 5.5 V 电压 - 压降（标准）:0.075V @ 400mA 稳压器数量:1 电流 - 输出:400mA（最小值） 电流 - 限制（最小）:400mA 工作温度:-55°C ~ 125°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:带卷 (TR) 其它名称:296-20789-2V62/06626-01XE |
| ISL80101IR50Z | 功能描述:IC REG LDO 5V 1A 10DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:3,000 系列:- 稳压器拓扑结构:正，可调式 输出电压:1.2 V ~ 5.5 V 输入电压:1.7 V ~ 5.5 V 电压 - 压降（标准）:0.075V @ 400mA 稳压器数量:1 电流 - 输出:400mA（最小值） 电流 - 限制（最小）:400mA 工作温度:-55°C ~ 125°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:带卷 (TR) 其它名称:296-20789-2V62/06626-01XE |
| ISL80101IR50Z-T | 功能描述:IC REG LDO 5V 1A 10DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:3,000 系列:- 稳压器拓扑结构:正，可调式 输出电压:1.2 V ~ 5.5 V 输入电压:1.7 V ~ 5.5 V 电压 - 压降（标准）:0.075V @ 400mA 稳压器数量:1 电流 - 输出:400mA（最小值） 电流 - 限制（最小）:400mA 工作温度:-55°C ~ 125°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:带卷 (TR) 其它名称:296-20789-2V62/06626-01XE |
| ISL80101IR50Z-TK | 功能描述:IC REG LDO 5V 1A 10DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:3,000 系列:- 稳压器拓扑结构:正，可调式 输出电压:1.2 V ~ 5.5 V 输入电压:1.7 V ~ 5.5 V 电压 - 压降（标准）:0.075V @ 400mA 稳压器数量:1 电流 - 输出:400mA（最小值） 电流 - 限制（最小）:400mA 工作温度:-55°C ~ 125°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:带卷 (TR) 其它名称:296-20789-2V62/06626-01XE |
| ISL80101IRAJZ | 功能描述:低压差稳压器 - LDO SINGLE 1A ADJ VOUTLD 3X3 10LD W/ANN RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
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