参数资料
| 型号： | ISL80102IRAJZ-TK |
| 厂商： | Intersil |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 2A 10DFN |
| 产品培训模块： | Solutions for Test and Measurement Equipment |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.8 V ~ 5 V |
| 输入电压： | 2.2 V ~ 6 V |
| 电压 - 压降（标准）： | 0.081V @ 2A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 2A（最小值） |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 标准包装 |
| 其它名称： | ISL80102IRAJZ-TKDKR |
ISL80102, ISL80103
Functional Description
Input Voltage Requirements
Despite other output voltages offered, this family of LDOs is
optimized for a true 2.5V to 1.8V conversion where the input
supply can have a tolerance of as much as ±10% for conditions
noted in the “Electrical Specifications” table on page 4. Minimum
guaranteed input voltage is 2.2V, however, due to the nature of
an LDO, V IN must be some margin higher than the output voltage
plus dropout at the maximum rated current of the application if
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
active filtering (PSRR) is expected from V IN to V OUT . The dropout
spec of this family of LDOs has been generously specified in
order to allow applications to design for a level of efficiency that
can accommodate the smaller outline package.
0.5
0
0
20
40
60
C SS (nF)
80
100
? R 3 ?
V OUT = 0.5V × ? ?
------- + 1
Enable Operation
The Enable turn-on threshold is typically 770mV with a hysteresis of
135mV. An internal pull-up or pull-down resistor is available upon
request. As a result, this pin must not be left floating. This pin must
be tied to V IN if it is not used. A 1k Ω to 10k Ω pull-up resistor is
required for applications that use open collector or open drain
outputs to control the Enable pin. The Enable pin may be connected
directly to V IN for applications that are always on.
Power-Good Operation
Applications not using this feature must connect this pin to
ground. The PGOOD flag is an open-drain NMOS that can sink up
FIGURE 39. IN-RUSH CURRENT vs SOFT-START CAPACITANCE
Output Voltage Selection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
programmed to any level between 0.8V and 5V. An external
resistor divider, R 3 and R 4 , is used to set the output voltage as
shown in Equation 1. The recommended value for R 4 is 500 Ω to
1k Ω. R 3 is then chosen according to Equation 2:
(EQ. 1)
? R 4 ?
R 3 = R 4 × ? ------------- – 1 ?
to 10mA during a fault condition. The PGOOD pin requires an
external pull-up resistor, which is typically connected to the VOUT
pin. The PGOOD pin should not be pulled up to a voltage source
V OUT
? 0.5V ?
(EQ. 2)
greater than V IN . The PGOOD fault can be caused by the output
voltage going below 84% of the nominal output voltage, or the
current limit fault, or low input voltage. The PGOOD does not
function during thermal shutdown. While the PGOOD functions in
shutdown.
Soft-Start Operation (Optional)
If the current limit for in-rush current is acceptable in the
application, do not use this feature. The soft-start circuit controls
the rate at which the output voltage comes up to regulation at
power-up or LDO enable. A constant current charges an external
soft-start capacitor. The external capacitor always gets
discharged to ground pin potential at the beginning of start-up or
enabling. The discharge rate is the RC time constant of R PD and
C SS . See Figures 26 through 29 in the “Typical Operating
Performance Curves” beginning on page 6. R PD is the
ON-resistance of the pull down MOSFET, M8. R PD is 300 Ω
typically.
The soft-start feature effectively reduces the in-rush current at
power-up or LDO enable until V OUT reaches regulation. The
in-rush current can be an issue for applications that require large,
external bulk capacitances on V OUT where high levels of charging
current can be seen for a significant period of time. The in-rush
currents can cause V IN to drop below minimum which could
cause V OUT to shutdown. Figure 39 shows the relationship
between in-rush current and C SS with a C OUT of 1000μF.
12
External Capacitor Requirements
External capacitors are required for proper operation. To ensure
optimal performance careful attention must be paid to the layout
guidelines and selection of capacitor type and value.
OUTPUT CAPACITOR
The ISL80102, ISL80103 applies state-of-the-art internal
compensation to keep selection of the output capacitor simple
for the customer. Stable operation over full temperature, V IN
range, V OUT range and load extremes are guaranteed for all
capacitor types and values assuming a 10μF X5R/X7R is used
for local bypass on V OUT . This minimum capacitor must be
connected to V OUT and Ground pins of the LDO with PCB traces
no longer than 0.5cm.
Lower cost Y5V and Z5U type ceramic capacitors are acceptable
if the size of the capacitor is larger to compensate for the
significantly lower tolerance over X5R/X7R types. Additional
capacitors of any value in Ceramic, POSCAP or Alum/Tantalum
Electrolytic types may be placed in parallel to improve PSRR at
higher frequencies and/or load transient AC output voltage
tolerances.
INPUT CAPACITOR
The minimum input capacitor required for proper operation is
10μF having a ceramic dielectric. This minimum capacitor must
be connected to V IN and ground pins of the LDO with PCB traces
no longer than 0.5cm.
FN6660.6
June 14, 2013
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相关代理商/技术参数 |
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| ISL80103 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High Performance 2A and 3A Linear Regulators |
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