参数资料
| 型号： | ISL80103IRAJZ-TK |
| 厂商： | Intersil |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 3A 10DFN |
| 产品培训模块： | Solutions for Test and Measurement Equipment |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.8 V ~ 5 V |
| 输入电压： | 2.2 V ~ 6 V |
| 电压 - 压降（标准）： | 0.12V @ 3A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 3A（最小值） |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 标准包装 |
| 其它名称： | ISL80103IRAJZ-TKDKR |
ISL80102, ISL80103
Phase Boost Capacitor (Optional)
The ISL80102 and ISL80103 are designed to be stable with
10μF or larger ceramic capacitor.
The maximum allowable junction temperature, T J(MAX) and the
maximum expected ambient temperature, T A(MAX) will determine the
maximum allowable power dissipation as shown in Equation 4:
Applications using the ADJ versions, may see improved
P D ( MAX ) = ( T J ( MAX ) – T A ) ? θ JA
(EQ. 4)
performance with the addition of a small ceramic capacitor C PB
as shown in Figure 2 on page 3. The conditions where C PB may
be beneficial are: (1) V OUT > 1.5V, (2) C OUT = 10μF, and (3) tight
AC voltage regulation band.
C PB introduces phase lead with the product of R 3 and C PB that
results in increasing the bandwidth of the LDO. Typical R3 x C PB
should be 4 μ s.
C PB not recommended for V OUT < 1.5V.
Current Limit Protection
The ISL80102, ISL80103 family of LDOs incorporates protection
against overcurrent due to short, overload condition applied to
the output and the in-rush current that occurs at start-up. The
LDO performs as a constant current source when the output
current exceeds the current limit threshold noted in the
“Electrical Specifications” table on page 4. If the short or
overload condition is removed from V OUT , then the output returns
to normal voltage mode regulation. In the event of an overload
condition, the LDO might begin to cycle on and off due to the die
temperature exceeding the thermal fault condition. The
TO220/TO263 package will tolerate higher levels of power
dissipation on the die which may never thermal cycle if the
heatsink of this larger package can keep the die temperature
below the specified typical thermal shutdown temperature.
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions (Note 8)” on page 4.
The power dissipation can be calculated by using Equation 3:
Where θ JA is the junction-to-ambient thermal resistance.
For safe operation, please make sure that power dissipation
calculated in Equation 3, P D be less than the maximum
allowable power dissipation P D(MAX) .
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for heat sinking. Figure 40 shows a curve for the θ JA
of the DFN package for different copper area sizes.
46
44
42
40
38
36
34
2 4 6 8 10 12 14 16 18 20 22 24
2
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
FIGURE 40. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS θ JA vs EPAD-MOUNT COPPER LAND
AREA ON PCB
Thermal Fault Protection
In the event the die temperature exceeds typically +160°C, then
the output of the LDO will shut down until the die temperature
can cool down to typically +145°C. The level of power combined
P D = ( V IN – V OUT ) × I OUT + V IN × I GND
13
(EQ. 3)
with the thermal impedance of the package (+48°C/W for DFN)
will determine if the junction temperature exceeds the thermal
shutdown temperature.
FN6660.6
June 14, 2013
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