参数资料
型号: ISL8012IRZ-T
厂商: Intersil
文件页数: 14/17页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A 10DFN
产品培训模块: Solutions for Test and Measurement Equipment
Solutions for Industrial Control Applications
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5.5 V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-VFDFN 裸露焊盘
包装: 标准包装
供应商设备封装: 10-DFN(3x3)
产品目录页面: 1248 (CN2011-ZH PDF)
其它名称: ISL8012IRZ-TDKR
ISL8012
V O ? ? 1 – --------- ? (EQ. 1)
L ? f S
performance. The inductor ripple current can be expressed as
shown in Equation 1:
? V O ?
? V IN ?
? I = ---------------------------------------
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL8012 protects the typical
peak current 3A. The saturation current needs be over 4A for
maximum output current application.
Output Voltage Selection
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier. Refer to Figure 1.
The output voltage programming resistor, R 3 , will depend on the
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10k ? and 100k ??? as shown in Equation 2.
R 3 = ----------------------------------
ISL8012 uses an internal compensation network and the output
capacitor value is dependent on the output voltage. The ceramic
R 2 ? 0.8V
V OUT – 0.8V
(EQ. 2)
capacitor is recommended to be X5R or X7R. The recommended
X5R or X7R minimum output capacitor values are shown in
Table 1.
TABLE 1. OUTPUT CAPACITOR VALUE vs V OUT
V OUT C OUT L
(V) (μF) (μH)
0.8 2x10 1.5~3.3
If the output voltage desired is 0.8V, then R 3 is left unpopulated
and R 2 is shorted. For better performance, add 220pF in parallel
with R 2 (124k ???
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current from flowing back to the
1.2
1.5
1.8
2.5
3.3
2x10
2x10
2x10
2x10
2x10
1.5~3.3
1.8~3.3
2.2~3.3
2.2~4.7
2.2~4.7
battery rail. Two 10μF X5R or X7R ceramic capacitors are a good
starting point for the input capacitor selection.
Layout Recommendation
The layout is a very important converter design step to make sure
the designed converter works well. For the ISL8012 buck
3.6 2x10 2.2~4.7
In Table 1, the minimum output capacitor value is given for the
different output voltage to make sure that the whole converter
system is stable. The maximum output capacitor should be
limited to 50μF or less.
14
converter, the power loop is composed of the output inductor L,
the output capacitor C OUT , LX pin and SGND pin. It is necessary to
make the power loop as small as possible.
The heat of the IC is mainly dissipated through the thermal pad.
Maximizing the copper area connected to the thermal epad is
preferable. In addition, a solid ground plane on the second layer
is helpful for EMI performance. Then connect the epad to the
ground plane with at least 5 vias for best thermal performance.
December 1, 2011
FN6616.2
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