参数资料
型号: ISL8022IRZ
厂商: Intersil
文件页数: 4/18页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ DL 12DFN
标准包装: 75
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.8 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 2.25MHz
电流 - 输出: 2A,1.7A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 12-VFDFN 裸露焊盘
包装: 管件
供应商设备封装: 12-DFN(4x3)
ISL8022
Ordering Information
Pin Configuration
PART NUMBER
(Notes 1, 2, 3)
ISL8022IRZ
PART
MARKING
8022
TEMP. RANGE
(°C)
-40 to +85
PACKAGE PKG.
(Pb-Free) DWG. #
12 Ld 4x3 DFN L12.4x3
ISL8022
(12 LD DFN)
TOP VIEW
ISL8022EVAL1Z Evaluation Board
ISL8022EVAL2Z Evaluation Board
FB1
EN1
1
2
12 FB2
11 EN2
NOTES:
1. Add “T” suffix for Tape and Reel. Please refer to TB347 for details
on reel specifications.
PG
VIN1
3
4
PAD
10 SYNC
9 VIN2
2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
LX1
PGND1
5
6
8
7
LX2
PGND2
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-
free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL8022 . For more information on MSL please see
techbrief TB363 .
Pin Description
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
-
SYMBOL
FB1
EN1
PG
VIN1
LX1
PGND1
PGND2
LX2
VIN2
SYNC
EN2
FB2
EXPOSED
PAD
DESCRIPTION
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The
output voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage
can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal
compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry
use FB1 to monitor the Channel 1 regulator output voltage.
Regulator Channel 1 enable pin. Enable the output, V OUT1 , when driven to high. Shutdown the V OUT1 and discharge output
capacitor when driven to low. Do not leave this pin floating.
1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the V OUT1 and V OUT2
voltages. There is an internal 1M Ω pull-up resistor.
Input supply voltage for Channel 1. Connect 10μF ceramic capacitor to PGND1.
Switching node connection for Channel 1. Connect to one terminal of inductor for V OUT1 .
Negative supply for power stage 1.
Negative supply for power stage 2 and system ground.
Switching node connection for Channel 2. Connect to one terminal of inductor for V OUT2 .
Input supply voltage for Ch 2 and to provide logic bias. Make sure that V IN2 is ≥ V IN1 . Connect 10μF ceramic capacitor to
PGND2.
Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM
mode. Connect to an external function generator for Synchronization. Negative edge trigger. Do not leave this pin floating.
Regulator Channel 2 enable pin. Enable the output, V OUT2 , when driven to high. Shutdown the V OUT2 and discharge output
capacitor when driven to low. Do not leave this pin floating.
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The
output voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage
can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal
compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry
use FB2 to monitor the Channel 2 regulator output voltage.
The exposed pad must be connected to the SGND pin for proper electrical performance. Add as much vias as possible for
optimal thermal performance.
4
FN7650.3
March 14, 2013
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