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| 型号： | ISL8024AIRTAJZ-T7A |
| 厂商： | Intersil |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 16TQFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.5 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 490kHz ~ 4.2MHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-TQFN（3x3） |
| 其它名称： | ISL8024AIRTAJZ-T7ADKR |
ISL8023, ISL8024
R2
Vo
C3
Example: V IN = 5V, V o = 1.8V, I o = 4A, f s = 1MHz,
C o = 2X22μF/3m Ω , L = 1μH, GM = 150μs, R t = 0.20V/A,
V FB = 0.6V, S e = 440mV/μs, S n = 6.4 × 10 5 V/s, f c = 100kHz, then
compensator resistance R 6 = 100k Ω .
R3
V FB
V REF
-
+
GM
V COMP
Put the compensator zero at 8kHz, and put the compensator pole
at either half of switching frequency or ESR zero. We choose
500kHz here, then the compensator capacitors are:
R6
C6
C7
C 6 = 220pF, C 7 = 3pF (There is approximately 3pF parasitic
capacitance from V COMP to GND; Therefore, C 7 optional).
Figure 43 shows the simulated voltage loop gain. It is shown that
it has 90kHz loop bandwidth with 70° phase margin and 10dB
gain margin.
FIGURE 42. TYPE II COMPENSATOR
Figure 42 shows the type II compensator and its transfer function
is expressed as Equation 14:
60
45
? 1 + ------------- ? ? 1 + ------------- ?
ω cz1 ? ?
ω cz2 ?
v ? comp
?
A v ( S ) = ----------------- = --------------------- ---------------------------------------------------------
v FB C 6 + C 7 S ? 1 + ---------- ?
ω cp
GM
S S
S
? ?
(EQ. 14)
30
15
0
where ,
ω cz1 = --------------- , ω cz2 = --------------- , ω cp = -----------------------
1 1 C 6 + C 7
R 6 C 6 R 2 C 3 R 6 C 6 C 7
-15
-30
100
1k
10k
100k
1M
Loop bandwidth f c : ? -- 4 - to ------ ? f s
Put compensator zero ω cz1 = ( 1to3 ) ---------------
R C
Compensator design goal:
High DC gain
? 1 1 ?
10
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is as follows:
1
o o
Put one compensator pole at zero frequency to achieve high DC
180
150
120
90
60
f (fi)
Put compensator zero ω cz2 = ( 5to8 ) ---------------
GM ? V FB
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower. An
optional zero can boost the phase margin. ω CZ2 is a zero due to
R 2 and C 3 .
1
R 2 C 3
The loop gain T v (S) at crossover frequency of f c has unity gain.
Therefore, the compensator resistance R 6 is determined by
Equation 15.
2 π f c V o C o R t
(EQ. 15)
R 6 = ----------------------------------
30
0
100
1k 10k 100k
f (fi)
FIGURE 43. SIMULATED LOOP GAIN
1M
where GM is the sum of the trans-conductance, g m , of the
voltage error amplifier in each phase. Compensator capacitor C6
is then given by Equation 16.
C 6 = --------------------- , C 7 = -------------------------
1 1
R 6 ω cz1 2 π R 6 f esr
(EQ. 16)
18
FN7812.3
March 24, 2014
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