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| 型号： | ISL8024IRTAJZ-T7A |
| 厂商： | Intersil |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 16TQFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.5 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 490kHz ~ 4.2MHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-TQFN（3x3） |
| 其它名称： | ISL8024IRTAJZ-T7ADKR |
ISL8023, ISL8024
Loop Compensation Design
Power Stage Transfer Functions
1 + ------------
v o ω esr
F 1 ( S ) = ------ = V in ---------------------------------------
d ?
------- + --------------- + 1
ω o Q p
ω o
When there is an external resistor connected from FS to SGND,
the COMP pin is active for external loop compensation. The
ISL8023, ISL8024 uses constant frequency peak current mode
control architecture to achieve fast loop transient response. An
accurate current sensing pilot device in parallel with the upper
MOSFET is used for peak current control signal and overcurrent
protection. The inductor is not considered as a state variable
Transfer function F 1 (S) from control to output voltage is:
S
2
S S
2
(EQ. 8)
1
1
Where ω esr = --------------- , Q p ≈ R o ------ o - , ω o = -------------------
since its peak current is constant, and the system becomes
single order system. It is much easier to design a type II
compensator to stabilize the loop than to implement voltage
mode control. Peak current mode control has inherent input
voltage feed-forward function to achieve good line regulation.
C
R c C o L P L P C o
Transfer function F 2 (S) from control to inductor current is given
by Equation 9:
L P
R LP
^
v o
1 + ------
F 2 ( S ) = ---- = ------------------------- ---------------------------------------
ω o Q p
ω o
Figure 41 shows the small signal model of the synchronous buck
regulator.
^ ^
i in i L
I
? o V in ω z
d R o + R LP S S
S
------- + --------------- + 1
2
(EQ. 9)
where ω z = --------------- .
+
^
V in
IL d ^
1:D
V in d ^
RT
Rc
1
R o C o
Current loop gain T i (S) is expressed as Equation 10:
Co
Ro
T i ( S ) = R t F m F 2 ( S ) H e ( S )
(EQ. 10)
The voltage loop gain with open current loop is Equation 11:
d ^
T i (S)
K
T v ( S ) = KF m F 1 ( S ) A v ( S )
(EQ. 11)
Fm
The Voltage loop gain with current loop closed is given by
+
He(S)
Tv (S)
Equation 12:
L v ( S ) = ------------------------
v ^ comp
-Av(S)
T v ( S )
1 + T i ( S )
(EQ. 12)
( S e + S n ) T s
v ? comp
S n = R t ---------------------
L
V FB
Where
FB is the feedback voltage of the voltage
1 + ------------
V FB R o + R LP ω esr A v ( S ) 1
L v ( S ) = ----------- ------------------------- ---------------------- ---------------- , ω p ≈ ---------------
S H e ( S )
FIGURE 41. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
PWM Comparator Gain F m :
The PWM comparator gain F m for peak current mode control is
given by Equation 5:
?
d 1 (EQ. 5)
F m = ----------------- = --------------------------------
Where S e is the slew rate of the slope compensation and S n is
given by Equation 6:
V in – V o (EQ. 6)
P
where R t is trans-resistance, which is the gain of the current
amplifier.
CURRENT SAMPLING TRANSFER FUNCTION H e (S):
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function in Equation 7:
K = ----------- , V
V o
error amplifier. If T i (S)>>1, then Equation 12 can be simplified as
Equation 13:
S
(EQ. 13)
V o R t 1 + ------- R o C o
ω p
Equation 13 shows that the system is a single order system,
which has a single pole located at ω p before the half switching
frequency. Therefore, a simple type II compensator can be easily
used to stabilize the system.
H e ( S ) = ------- + --------------- + 1
ω n Q n
ω n
where Q n and ω n are given by Q n = – --- , ω n = π f s
S S
2
2
2
π
(EQ. 7)
17
FN7812.3
March 24, 2014
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