参数资料
| 型号： | ISL8036IRZ |
| 厂商： | Intersil |
| 文件页数： | 22/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 24QFN |
| 标准包装： | 75 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 或 2 |
| 输出电压： | 0.8 V ~ 6 V |
| 输入电压： | 2.85 V ~ 6 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-QFN（4x4） |
ISL8036, ISL8036A
Theory of Operation
The ISL8036, ISL8036A is a dual 3A or current sharing 6A
step-down switching regulator optimized for battery-powered or
mobile applications. The regulator operates at 1MHz (ISL8036) or
2.5MHz (ISL8036A) fixed switching frequency under heavy load
condition. The two channels are 180° out-of-phase operation. The
supply current is typically only 8μA when the regulator is shutdown.
PWM Control Scheme
Pulling the SYNC pin HI (>1.5V) forces the converter into PWM mode
in the next switching cycle regardless of output current. Each of the
channels of the ISL8036, ISL8036A employ the current-mode
pulse-width modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting, as shown in the “Block
consists of the oscillator, the PWM comparator COMP, current
sensing circuit, and the slope compensation for the current loop
stability. The current sensing circuit consists of the resistance of the
P-channel MOSFET when it is turned on and the current sense
amplifier CSA1. The gain for the current sensing circuit is typically
0.2V/A. The control reference for the current loops comes from the
error amplifier EAMP of the voltage loop.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA1 (or CSA2 on Channel 2) and the
compensation slope (0.46V/μs) reaches the control reference of
the current loop, the PWM comparator COMP sends a signal to the
PWM logic to turn off the P-MOSFET and to turn on the N-channel
MOSFET. The N-MOSFET stays on until the end of the PWM cycle.
Figure 66 shows the typical operating waveforms during the PWM
operation. The dotted lines illustrate the sum of the compensation
ramp and the current-sense amplifier CSA_ output.
V EAMP
V CSA1
Duty
Cycle
I L
V OUT
FIGURE 66. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a 0.8V
reference voltage to the voltage control loop. The feedback signal
comes from the VFB pin. The soft-start block only affects the
operation during the start-up and will be discussed separately.
The error amplifier is a transconductance amplifier that converts
the voltage error signal to a current output. The voltage loop is
internally compensated with the 27pF and 390k ? RC network.
The maximum EAMP voltage output is precisely clamped to the
bandgap voltage (1.172V).
22
Synchronization Control
The frequency of operation can be synchronized up to 6MHz by
an external signal applied to the SYNC pin. The 1st falling edge
on the SYNC triggered the rising edge of the PWM ON pulse of
Channel 1. The 2nd falling edge of the SYNC triggers the rising
edge of the PWM ON pulse of the Channel 2. This process
alternate indefinitely allowing 180° output phase operation
between the two channels.
Output Current Sharing
The ISL8036, ISL8036A dual outputs are paralleled for
multi-phase operation in order to support a 6A output. Connect
the FBs together and connect all the COMPs together. Channel 1
and Channel 2 will be 180° out-of-phase. In parallel configuration,
external soft-start should be used to ensure proper full loading
start-up. Before using full load in current sharing mode, PWM
mode should be enabled. Likewise, multiple regulators can be
paralleled by connecting the FBs, COMPs, and SS for higher
current capability. External compensation is required.
Overcurrent Protection
CAS1 and CSA2 are used to monitor Output 1 and Output 2
channels respectively. The overcurrent protection is realized by
monitoring the CSA output with the OCP threshold logic, as
shown in Figure 4. The current sensing circuit has a gain of
0.2V/A, from the P-MOSFET current to the CSA_ output. When
the CSA1 output reaches the threshold, the OCP comparator is
tripped to turn off the P-MOSFET immediately. The overcurrent
function protects the switching converter from a shorted output by
monitoring the current flowing through the upper MOSFETs.
Upon detection of overcurrent condition, the upper MOSFET will
be immediately turned off and will not be turned on again until
the next switching cycle. Upon detection of the initial overcurrent
condition, the Overcurrent Fault Counter is set to 1 and the
Overcurrent Condition Flag is set from LOW to HIGH. If, on the
subsequent cycle, another overcurrent condition is detected, the
OC Fault Counter will be incremented. If there are 17 sequential
OC fault detections, the regulator will be shutdown under an
Overcurrent Fault Condition. An Overcurrent Fault Condition will
result with the regulator attempting to restart in a hiccup mode
with the delay between restarts being 8 soft-start periods. At the
end of the eighth soft-start wait period, the fault counters are
reset and soft-start is attempted again. If the overcurrent
condition goes away prior to the OC Fault Counter reaching a
count of four, the Overcurrent Condition Flag will set back to LOW.
If the negative output current reaches -2.5A, the part enters
Negative Overcurrent Protection. At this point, all switching stops
and the part enters tri-state mode while the pull-down FET is
discharging the output until it reaches normal regulation voltage,
then the IC restarts.
PG
There are two independent power-good signals. PG1 monitors
the Output Channel 1 and PG2 monitors the Output Channel 2.
When powering up, the open-collector Power-on Reset output
holds low for about 1ms after V O reaches the preset voltage. The
PG_ output also serves as a 1ms delayed Power-Good signal.
FN6853.3
August 17, 2012
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