参数资料
型号: ISL8104IRZ
厂商: Intersil
文件页数: 12/14页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16-QFN
标准包装: 75
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 100%
电源电压: 7.6 V ~ 15.4 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 管件
ISL8104
Standard-gate MOSFETs are normally recommended for
use with the ISL8104. However, logic-level gate MOSFETs
+14V
D BOOT
can be used under special circumstances. The input voltage,
top-side gate drive level, and the MOSFETs absolute gate-
+
V D
-
+1.2V TO +14V
to-source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the top-side gate drive (BOOT pin) supplied
by a bootstrap circuit from +14V. The boot capacitor, C BOOT
develops a floating supply voltage referenced to the LX pin.
ISL8104
BOOT
TGATE
LX
C BOOT
Q1
NOTE:
V G-S ≈ V CC - V D
PVCC
This supply is refreshed each cycle to a voltage of +14V less
the boot diode drop (V D ) when the bottom-side MOSFET, Q 2
turns on. A MOSFET can only be used for Q 1 if the
MOSFETs absolute gate-to-source voltage rating exceeds
the maximum voltage applied to +14V. For Q 2 , a logic-level
-
+
+14V
BGATE
PGND
Q2
D2
NOTE:
V G-S ≈ PVCC
MOSFET can be used if its absolute gate-to-source voltage
rating also exceeds the maximum voltage applied to +14V.
Figure 10 shows the top-side gate drive supplied by a direct
connection to +14V. This option should only be used in
converter systems where the main input voltage is +5VDC or
less. The peak top-side gate-to-source voltage is
approximately +14V less the input supply. For +5V main
GND
FIGURE 9. TOP-SIDE GATE DRIVE - BOOTSTRAP OPTION
power and +14VDC for the bias, the gate-to-source voltage
of Q 1 is 9V. A logic-level MOSFET is a good choice for Q 1
and a logic-level MOSFET can be used for Q 2 if its absolute
gate-to-source voltage rating exceeds the maximum voltage
+14V
ISL8104
BOOT
+5V OR LESS
applied to PVCC. This method reduces the number of
required external components, but does not provide for
immunity to phase node ringing during turn on and may
result in lower system efficiency.
Schottky Selection
TGATE
PVCC
+14V
Q1
NOTE:
V G-S ≈ V CC - 5V
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the bottomside
MOSFET and turning on the top-side MOSFET. The diode
-
+
BGATE
PGND
Q2
D2
NOTE:
V G-S ≈ PVCC
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to omit
the diode and let the body diode of the bottom-side MOSFET
clamp the negative inductor swing, but efficiency could slightly
decrease as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
12
GND
FIGURE 10. TOP-SIDE GATE DRIVE - DIRECT V CC DRIVE
OPTION
FN9257.2
March 7, 2008
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