参数资料
型号: ISL8105BEVAL2Z
厂商: Intersil
文件页数: 3/11页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL8105B
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.8V
电流 - 输出: 15A
输入电压: 9.6 ~ 14.4V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL8105B
Application Note 1288
With Infineon’s BSC030N03LS as the low-side MOSFET and
R BSOC of 1.74k Ω . The overcurrent trip point on the evaluation
3. Select C 1 such that F Z1 is located at 1.5kHz (~50% of
F LC ):
C 1 = --------------------------------------------
2 π ? R 2 ? 1.5 × 10
board has been set to 21A for 12V BIAS (17A for 5V BIAS ).
C 2
1
≈ 10nF
3
(EQ. 18)
2 π ? R 2 ? C 1 ? F ESR – 1
COMP
R 2
E/A
-
+
C 1
FB
R 3
R 4
R 1
C 3
4. Select C 2 such that F P1 is located at F ESR :
C 1
C 2 = ------------------------------------------------------------
≈ 390pF
(EQ. 19)
VREF
5. Select R 3 such that F Z2 is located at F LC :
R 3 = -------------------------------- ≈ 301 Ω
150 × 10
C 3 = ---------------------------------------------- ≈ 3.3nF
2 π ? R 3 ? 150 × 10
PWM
OSCILLATOR
V OSC
V IN
V OUT
R 1
3
---------------------- – 1
F LC
1
3
(EQ. 20)
CIRCUIT
A more detailed explanation of designing compensation
HALF-BRIDGE
TGATE
L
DCR
networks for buck converters with voltage mode control can
be found in TB417 entitled “Designing Stable Compensation
DRIVE
ISL8105B
LX
BGATE
EXTERNAL CIRCUIT
C
ESR
Networks for Single Phase Voltage Mode Buck Regulators”.
Evaluation Board Performance
Figure 2 shows a photograph of the ISL8105BEVAL1Z.
FIGURE 1. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Feedback Compensator
Type-III network is recommended for compensating the
feedback loop. Figure 1 shows Type-III compensation
configuration for ISL8105B.
With the inductor and output capacitor selected as described
in the previous sections, the poles and zero of the power
stage can be summarized in Equation 15:
F 0 = ------------------------------------- = 3.7kHz
F ESR = ------------------------------------------- = 33.9kHz
1
2 × π × L × C
1
2 × π × C × ESR
(EQ. 15)
FIGURE 2. ISL8105BEVAL1Z
1. With a value of 11.8k Ω for R 1 , select R 4 for the target
output voltage of 1.8V using Equation 16:
Power and Load Connections
R 4 = R 1 × ---------------------------------
V – V
V ref
OUT ref
= 5.9k Ω
(EQ. 16)
Terminals J1 and J2 are connected to the input of the power
stage. The IC bias supply and the converter input supply can
be together through pin 2 and 3 of the Jumper J7 to provide
single rail supply application. When using separate supplies,
2. With the desired feedback loop bandwidth of 30kHz, R 2
can be calculated using Equation 17:
provide the IC bias voltage to terminal J2 with pin 2 and pin 1
of J7 connected together. The load can be connected to
d max ? V IN ? F LC
V OSC ? R 1 ? F 0
R 2 = --------------------------------------------
= 12k Ω
3
(EQ. 17)
terminal J4 and J5. TP6 and TP3 can be used for DMM to
measure output voltage. The scope probe terminal (TPV01)
can be used to monitor V OUT with an oscilloscope. The push
switch, SW1, can be used to disable the controller.
AN1288.1
October 30, 2008
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