参数资料
型号: ISL8120EVAL4Z
厂商: Intersil
文件页数: 33/35页
文件大小: 0K
描述: BOARD EVALUATION FOR ISL8120
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.2V
电流 - 输出: 50A
输入电压: 12V
稳压器拓扑结构: 降压
频率 - 开关: 1.5MHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL8120
ISL8120
VSENSE- (REMOTE)
VOUT (LOCAL)
10 Ω
VSENSE+ (REMOTE)
GND (LOCAL)
10 Ω
C SEN
R OS
R FB
Z FB
Z COMP
VCC
VSEN-
VSEN+
VMON
FB
COMP
PGOOD
700mV
GAIN=1
V REF
OV/UV
COMP
ERROR AMP
PGOOD
FIGURE 24. SIMPLIFIED REMOTE SENSING IMPLEMENTATION
Since the UV/OV comparator uses the same internal reference
0.6V, to guarantee UV/OV and Pre-charged start-up functions
of Channel 2, the target voltage derived from Channel 1
(VDDQ) should be scaled close to 0.6V, and it is suggested to
VDDQ
PHASE-SHIFTED
CLOCK
VCC
VSEN2-
be slightly above (+2%) 0.6V with an external resistor divider,
ISL8120
which will have Channel 2 use the internal 0.6V reference after
soft-start. Any capacitive load at REFIN pin should not slow
k*R
CLKOUT/REFIN
STATE
MACHINE
down the ramping of this input 150mV lower than the Channel
k = ------------ – 1
2’ internal ramp. Otherwise, the UV protection could be fault
triggered prior to the end of the soft-start. The start-up of
Channel 2 can be delayed to avoid such situation happening, if
high capacitive load presents at REFIN pin for noise
decoupling. During shutdown, Channel 2 will follow Channel 1
R
VTT
0.6V
700mV
until both channels drops below 87%, at which point both
Internal SS
0.6V
channels enter UV protection zone. Depending on the loading,
Channel 1 might drop faster than Channel 2. To solve this race
FB2
E/A2
condition, Channel 2 can either power up from Channel 1 or
bridge the Channel 1 with a high current Schottky diode. If the
system requires to shutdown both channels when either has a
fault, tying EN/FF1 and EN/FF2 will do the job. In DDR mode,
Channel 1 delays 60° over Channel 2.
In Dual mode, depending upon the resistor divider level of
REFIN from VCC, the ISL8120 operates as a dual-PWM
controller for two independent regulators with a phase shift,
as shown in Table 2. The phase shift is latched as VCC
raises above POR and cannot be changed on the fly.
TABLE 2.
FIGURE 25. SIMPLIFIED DDR IMPLEMENTAION
Internal Reference and System Accuracy
The internal reference is set to 0.6V. Including bandgap
variation and offset of differential and error amplifiers, it has
an accuracy of ±0.6% over commercial temperature range,
and 0.9% over industrial temperature range. While the
remote sense is not used, its offset (V OS_DA ) should be
included in the tolerance calculation. Equations 9 and 10
show the worst case of system accuracy calculation.
V OS_DA should set to zero when the differential amplifier is
in the loop, the differential amplifier ’s input impedance
MODE
DDR
DECODING
REFIN RANGE
<29% of VCC
PHASE for CHANNEL REQUIRED
2 WRT CHANNEL 1 REFIN
-60° 0.6V
(R DIF ) is typically 500k Ω with a tolerance of 20% (RDIF%)
and can be neglected when R OS is less than 100 Ω . To set a
precision setpoint, R OS can be scaled by two paralleled
Dual
Dual
Dual
29% to 45% of VCC
45% to 62% of VCC
62% to VCC
90°
180°
37% VCC
53% VCC
VCC
resistors.
F igure 26 shows the tolerance of various output voltage
regulation for 1%, 0.5%, and 0.1% feedback resistor
33
March 20, 2009
FN6641.0
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