参数资料
型号: ISL8120IRZ-TEC
厂商: Intersil
文件页数: 29/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 22 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL8120IR
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
P Qg_Q1 = --------------------------------------- ? F SW ? N Q1
P Qg_Q2 = --------------------------------------- ? F SW ? N Q2
P DR = P DR_UP + P DR_LOW
? R HI1 R LO1 ? P Qg_Q1
? R HI2 R LO2 ? P Qg_Q2
Q G1 ? PVCC 2
V GS1
Q G2 ? PVCC 2
V GS2
2
2
(EQ. 8)
Oscillator
The Oscillator is a sawtooth waveform, providing for leading
edge modulation with 350ns minimum dead time. The
oscillator (Sawtooth) waveform has a DC offset of 1.0V.
Each channel’s peak-to-peak of the ramp amplitude is set to
proportional the voltage applied to its corresponding EN/FF
1,600
1,400
1,200
1,000
800
R EXT2 = R G1 + -------------
N
R EXT2 = R G2 + -------------
N
R GI1
Q1
R GI2
Q2
600
400
where the gate charge (Q G1 and Q G2 ) is defined at a
particular gate to source voltage (V GS1 and V GS2 ) in the
corresponding MOSFET datasheet; I Q_VIN is the driver ’s
total quiescent current with no load at drive outputs; N Q1 and
N Q2 are number of upper and lower MOSFETs, respectively.
To keep the IC within its operating temperature range, an
external power resistor could be used in series with VIN pin
to bring the heat out of the IC, or and external LDO could be
used when necessary.
200
0
20 40 60 80 100 120 140 160 180 200 220 240 260
R_FS (k Ω )
FIGURE 20. R FS vs SWITCHING FREQUENCY
Frequency Synchronization and Phase Lock Loop
The FSYNC pin has two primary capabilities: fixed frequency
operation and synchronized frequency operation. By tying a
resistor (R FSYNC ) to GND from FSYNC pin, the switching
frequency can be set at any frequency between 150kHz and
PVCC
BOOT
C GD
D
1.5MHz. Frequency setting curve shown in Figure 20 are
provided to assist in selecting the correct value for R FSYNC .
By connecting the FSYNC pin to an external square pulse
R HI1
G
C DS
waveform (such as the CLOCK signal, typically 50% duty
cycle from another ISL8120IRZEC), the ISL8120IRZEC will
R LO1
UGATE
R G1
R GI1
C GS
Q1
synchronize its switching frequency to the fundamental
frequency of the input waveform. The maximum voltage to
S
PHASE
FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
C GD
FSYNC pin is VCC + 0.3V. The Frequency Synchronization
feature will synchronize the leading edge of CLKOUT signal
with the falling edge of Channel 1’s PWM clock signal. The
CLKOUT is not available until the PLL locks.
The locking time is typically 130μs for F SW = 500kHz.
EN/VFF1 is released for a soft-start cycle until the FSYNC
stabilized and the PLL is in locking. The PLL circuits control
only EN/FF1, and control Channel 2’s soft-start instead of
EN/FF2. Therefore, it is recommended to connect all EN/FF
R HI2
R LO2
LGATE
G
R G2
R GI2
C DS
pins together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles, the
GND
C GS
S
Q2
IC is disabled until the PLL returns locking, at which point a
soft-start cycle is initiated and normal operation resumes.
Holding FSYNC low will disable the IC.
FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
29
FN6763.2
November 11, 2011
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