参数资料
型号: ISL8126CRZ-T7A
厂商: Intersil
文件页数: 3/39页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 5.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 标准包装
其它名称: ISL8126CRZ-T7ADKR
ISL8126
Functional Pin Descriptions (Continued)
PIN
NUMBER
4, 6
5
7
8
32, 10
31, 11
30, 12
SYMBOL
EN/VFF1, EN/VFF2
FSYNC
CLKOUT/REFIN
PGOOD
FB1, FB2
VMON1, VMON2
VSEN1-, VSEN2-
3
DESCRIPTION
These pins have triple functions. The voltage on EN/VFF_ pin is compared with a precision 0.8V threshold
for system enable to initiate soft-start. With a voltage lower than the threshold, the corresponding channel
can be disabled independently. By connecting these pins to the input rail through a voltage resistor divider,
the input voltage can be monitored for UVLO (undervoltage lockout) function. The undervoltage lockout and
its hysteresis levels can be programmed by these resistor dividers. The voltages on these pins are also fed
into the controller to adjust the sawtooth amplitude of each channel independently to realize the feed-
forward function.
Furthermore, during fault (such as overvoltage, overcurrent, and over-temperature) conditions, these pins
(EN/VFF_) are pulled low to communicate the information to other cascaded ICs.
The oscillator switching frequency is adjusted by placing a resistor (RFS) from this pin to GND. The internal
oscillator will lock to an external frequency source if this pin is connected to a switching square pulse
waveform, typically the CLKOUT signal from another ISL8126 or an external clock. The internal oscillator
synchronizes with the leading edge of the input signal.
This pin has a dual function depending on the mode in which the chip is operating. It provides a clock signal
to synchronize with other ISL8126(s) with its VSEN2- pulled within 400mV of VCC for multiphase (3-, 4-, 6-,
8-, 10-, or 12-phase) operation. When the VSEN2- pin is not within 400mV of VCC, ISL8126 is in dual mode
(dual independent PWM output). The clockout signal of this pin is not available in this mode, but the
ISL8126 can be synchronized to external clock. In dual mode, this pin works as the following two functions:
1. An external reference (0.6V target only) can be in place of the Channel 2’s internal reference through
this pin for DDR/tracking applications.
2. The ISL8126 operates as a dual-PWM controller for two independent regulators with selectable phase
degree shift, which is programmed by the voltage level on REFIN (see DDR and Dual Mode
Provides an open drain Power-Good signal when both channels are within 9% of the nominal output
regulation point with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs
(VMON1/2) of the internal differential amplifiers.
These pins are the inverting inputs of the error amplifiers. These pins should be connected to VMON1,
VMON2 with the compensation feedback network. No direct connection between FB and VMON pins is
allowed. With VSEN2- pulled within 400mV of VCC, the corresponding error amplifier is disabled and the
amplifier’s output is high impedance. FB2 is one of the two pins to determine the relative phase
relationship between the internal clock of both channels and the CLKOUT signal. See Table 2 on page 23.
These pins are outputs of the differential amplifiers. They are connected internally to the OV/UV/PGOOD
comparators. These pins should be connected to the FB1, FB2 pins by a standard feedback network when
both channels are operating independently. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the
corresponding differential amplifier is disabled and its output (VMON pin) is high impedance. In such an
event, the VMON pins can be used as additional monitors of the output voltage with a resistor divider to
protect the system against single point of failure, which occurs in the system using the same resistor
divider for both of the UV/OV comparator and output voltage feedback.
These pins are the negative inputs of standard unity gain operational amplifier for differential remote
sense for the corresponding regulator (Channels 1 and 2), and should be connected to the negative rail of
the load.
When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding error amplifier and differential
amplifier are disabled and their outputs are high impedance. Both VSEN2+ and FB2 input signal levels
determine the relative phases between the internal controllers as well as the CLKOUT signal. See Table 2
When configured as multiple power modules (each module with independent voltage loop) operating in
parallel, in order to implement the current sharing control, a resistor needs to be inserted between the
VSEN1- pin and the output voltage negative sense point (between VSEN1- and lower voltage sense resistor),
as shown in the “Typical Application Circuits” Multiple Power Modules in Parallel with Current Sharing
Control on page 14. This introduces a correction voltage for the modules with lower load current to keep
the current distribution balanced among modules. The module with the highest load current will
automatically become the master module. The recommended value for the VSEN1- resistor is 100 Ω and it
should not be large in order to keep the unit gain amplifier input impedance compatibility. A capacitor is
also recommended to place in parallel with the 100 Ω .
FN7892.1
August 16, 2012
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