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| 型号： | ISL8126CRZ |
| 厂商： | Intersil |
| 文件页数： | 36/39页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-QFN |
| 标准包装： | 60 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 90% |
| 电源电压： | 3 V ~ 5.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL8126
DDR and Dual Mode Operation
When ISL8126 is used in dual-output mode, the CLKOUT/REFIN
pin is an input signal pin. If the CLKOUT/REFIN is less than 29%
of VCC, an external soft-start ramp (0.6V) can be in parallel with
Channel 2s internal soft-start ramp for DDR/tracking
applications (DDR Mode).
VDDQ
k*R
PHASE-SHIFTED
CLOCK
CLKOUT/REFIN
VCC
VSEN2-
ISL8126
STATE
MACHINE
The output voltage (typical VTT output) of Channel 2 tracks with
the input voltage (typical VDDQ*(1+k) from Channel 1) at the
CLKOUT/REFIN pin. As for the external input signal and internal
reference signal (ramp and 0.6V), the one with the lowest voltage
R
400mV
k = ------------ – 1
will be the one to be used as the reference compared with the FB
signal. So in DDR configuration, VTT channel should start-up later
after its internal soft-start ramp, in which way, the VTT will track
the voltage on REFIN pin derived from VDDQ. This can be
achieved by adding more filtering at EN/VFF1 compared with
VTT
0.6V
Internal SS
0.6V
FB2
E/A2
EN/VFF2.
Since the UV/OV comparator uses the same internal reference 0.6V
to guarantee UV/OV and Pre-charged start-up functions of
Channel 2, the target voltage derived from Channel 1 (VDDQ) should
be scaled close to 0.6V, and it is suggested to be slightly above
(+2%) 0.6V with an external resistor divider, which will have
Channel 2 use the internal 0.6V reference after soft-start. Any
capacitive load at the REFIN pin should not slow down the ramping
of this input 150mV lower than the Channel 2’s internal ramp.
Otherwise, the UV protection could be fault triggered prior to the end
of the soft-start. The start-up of Channel 2 can be delayed to avoid
such a situation from happening, if high capacitive load presents at
REFIN pin for noise decoupling. During shutdown, Channel 2 will
follow Channel 1 until both channels drops below 87%, at which
point both channels enter UV protection zone. Depending on the
loading, Channel 1 might drop faster than Channel 2. To solve this
race condition, Channel 2 can either power up from Channel 1 or
bridge the Channel 1 output with a high current Schottky diode. If
the system requires to shutdown both channels when either has a
fault, tying EN/VFF1 and EN/VFF2 will do the job. In DDR mode,
Channel 1 delays 60° over Channel 2.
In Dual mode, depending upon the resistor divider level of REFIN
from VCC, the ISL8126 operates as a dual-PWM controller for
two independent regulators with a phase shift, as shown in
Table 3. The phase shift is latched as VCC raises above POR and
cannot be changed on the fly.
TABLE 3.
DECODING PHASE for CHANNEL 2 REQUIRED
MODE REFIN RANGE WRT CHANNEL 1 REFIN
DDR <29% of VCC -60° 0.6V
FIGURE 33. SIMPLIFIED DDR IMPLEMENTATION
minimizes these voltage spikes. Consider, as an example, the
turnoff transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying current. During the turnoff, current
stops flowing in the upper MOSFET and is picked up by the lower
MOSFET. Any inductance in the switched current path generates
a large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components, and
short, wide circuit traces minimize the magnitude of voltage
spikes.
There are two sets of critical components in a DC/DC converter
using a ISL8126 controller. The power components are the most
critical because they switch large amounts of energy. Next, are
small signal components that connect to sensitive nodes or
supply critical bypassing current and signal coupling.
The power components should be placed first, which include the
MOSFETs, input and output capacitors, and the inductors. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally across
all power trains. Equidistant placement of the controller to the
power trains (it controls through the integrated drivers), helps
keep the gate drive traces equally short, resulting in equal trace
impedances and similar drive capability of all sets of MOSFETs.
When placing the MOSFETs, try to keep the source of the upper
FETs and the drain of the lower FETs as close as thermally
possible. Input high-frequency capacitors, C HF , should be placed
close to the drain of the upper FETs and the source of the lower
Dual
Dual
Dual
29% to 45% of VCC
45% to 62% of VCC
62% to VCC
0°
90°
180°
37% VCC
53% VCC
VCC
FETs. Input bulk capacitors, C BULK , case size typically limits
following the same rule as the high-frequency input capacitors.
Place the input bulk capacitors as close to the drain of the upper
FETs as possible and minimize the distance to the source of the
Layout Considerations
MOSFETs switch very fast and efficiently. The speed at which the
current transitions from one device to another causes voltage
spikes across the interconnecting impedances and parasitic
circuit elements. These voltage spikes can degrade efficiency,
radiate noise into the circuit and lead to device overvoltage
stress. Careful component selection, layout, and placement
36
lower FETs.
Locate the output inductors and output capacitors between the
MOSFETs and the load. The high-frequency output decoupling
capacitors (ceramic) should be placed as close as practicable to
the decoupling target, making use of the shortest connection
paths to any internal planes, such as vias to GND next or on the
capacitor solder pad.
FN7892.1
August 16, 2012
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL8126CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8126CRZ-T7A | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
| ISL8126IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8126IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8126IRZ-T7A | 制造商:Intersil Corporation 功能描述:SCALABLE 2-PHASE CONTROLLER W/INTEGRATED DRIVERS, IND, 32LD - Tape and Reel 制造商:Intersil Corporation 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN |
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