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参数资料
| 型号： | ISL8126IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 34/39页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 90% |
| 电源电压： | 3 V ~ 5.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL8126
VSENSE- (REMOTE)
VOUT (LOCAL)
10 Ω
VSENSE+ (REMOTE)
GND (LOCAL)
10 Ω
C SEN
R OS
R FB
Z FB
Z COMP
VCC
VSEN-
VSEN+
VMON
FB
COMP
PGOOD
400mV
GAIN=1
V REF
OV/UV
COMP
ERROR AMP
PGOOD
FIGURE 29. SIMPLIFIED REMOTE SENSING IMPLEMENTATION
1,600
1,400
1,200
1,000
800
600
400
200
Differential Amplifier for Remote Sensing
The differential remote sense buffers help compensate the droop
due to load on the positive and negative rails and maintain the
high system accuracy of ±0.6%. They have precision unity gain
resistor matching networks, which has a ultra low offset of 1mV.
The output of the remote sense buffer is connected directly to the
internal OV/UV comparator. As a result, a resistor divider should
be placed on the input of the buffer for proper regulation, as
shown in Figure 29. The VMON pin should be connected to the FB
pin by a standard feedback network. The output voltage can be
V OUT = V ref ? ? 1 + ---------- ?
.
0
20 40 60 80 100 120 140 160 180 200 220 240 260
R_FS (k Ω )
FIGURE 28. R FS vs SWITCHING FREQUENCY
set by using Equation 18:
? R FB ?
? R OS ?
(EQ. 18)
R FSYNC [ k Ω ] = 4.671 × 10 ? Fsw [ kHz ]
(EQ. 17)
4 – 1.04
By connecting the FSYNC pin to an external square pulse
waveform (such as the CLOCK signal, typically 50% duty cycle
from another ISL8126), the ISL8126 will synchronize its
switching frequency to the fundamental frequency of the input
waveform. The maximum voltage to the FSYNC pin is VCC + 0.3V.
The Frequency Synchronization feature will synchronize the
leading edge of CLKOUT signal with the falling edge of
Channel 1’s PWM clock signal. The CLKOUT is not available until
To optimize system accuracy, it is highly recommended to
include this impedance into calculation and use resistor with
resistance as low as possible for the lower leg (R OS ) of the
feedback resistor divider. Note that any RC filter at the inputs of
the differential amplifier, will contribute as a pole to the overall
loop compensation.
VCC
I = VSEN + + 1.16μA
40k
the PLL locks.
VSEN+
20k
The locking time is typically 130μs for F SW = 500kHz. EN/VFF1 is
pulled down internally until the FSYNC stabilized and the PLL is in
locking. The PLL circuits control only EN/VFF1, and control the
R DIF = -500k
1.16μA
20k
delay time of Channel 2’s soft-start. Therefore, it is
recommended to connect all EN/VFF pins together in multiphase
configuration.
VSEN-
20k
20k
The loss of a synchronization signal for 13 clock cycles causes
the IC to be disabled until the PLL returns locking, at which point
a soft-start cycle is initiated and normal operation resumes.
Holding FSYNC low will disable the IC.
34
FIGURE 30. EQUIVALENT DIFFERENTIAL AMPLIFER
FN7892.1
August 16, 2012
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL8126IRZ-T7A | 制造商:Intersil Corporation 功能描述:SCALABLE 2-PHASE CONTROLLER W/INTEGRATED DRIVERS, IND, 32LD - Tape and Reel 制造商:Intersil Corporation 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN |
| ISL8126IRZ-TK | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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| ISL8130 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced Single Universal Pulse-Width Modulation (PWM) Controller |
| ISL8130EVAL3Z | 制造商:Intersil Corporation 功能描述:ISL8130 EVALUATION BOARD 3 - 20LD QSOP - ROHS COMPLIANT - Bulk 制造商:Intersil Corporation 功能描述:BOARD EVAL FOR ISL8130 制造商:Intersil Corporation 功能描述:ISL8130 EVALUATION BOARD 3 - 20LD QSOP - RoHS COMPLIANT |
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