参数资料
型号: ISL8130IAZ
厂商: Intersil
文件页数: 21/24页
文件大小: 0K
描述: IC REG CTRLR BST FLYBK VM 20QSOP
标准包装: 58
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-SSOP(0.154",3.90mm 宽)
包装: 管件
ISL8130
2 π ? ( I OUT ? L BST )
F Z1 = ----------------------------------
2 π ? R 2 ? C1
The right-half-plane zero is a function of load current, VIN and the
boost inductance. The RHP zero causes phase lag decreasing
phase margin. It is recommended to have the closed loop gain
cross 0dB at 1/3 of the F RHP (Equation 33).
V IN ? ( 1 – DC )
F RHP = --------------------------------------------------- (EQ. 33)
Compensation Break Frequency Equations
1
(EQ. 34)
Figure 35 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying the
modulator transfer function to the compensation transfer function
and plotting the gain.
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1 ST Zero Below Filter’s Double Pole (~75% F LC )
3. Place 2 ND Zero at Filter’s Double Pole
4. Place 1 ST Pole at the right half plane zero, F RHP
5. Place 2 ND Pole at Half the Switching Frequency
F P1 = -------------------------------------------------------
2 π ? R2 ? ? ---------------------- ?
F Z2 = ------------------------------------------------------
1
C1 ? C2
? C1 + C2 ?
1
2 π ? ( R1 + R3 ) ? C3
(EQ. 35)
(EQ. 36)
6. Check Gain against Error Amplifier’s Open-Loop Gain
Estimate Phase Margin - Repeat if Necessary
In applications when the RHP zero makes the stabilizing the
converter very difficult, it is recommended to increase the output
capacitor.
F P2 = ----------------------------------
1
2 π ? R3 ? C3
The compensation network consists of the error amplifier
(EQ. 37)
100
F Z 1 F Z2
F P1
F P2
(internal to the ISL8130) and the impedance networks Z IN and
Z FB . The goal of the compensation network is to provide a closed
loop transfer function with the highest 0dB crossing frequency
80
60
OPEN LOOP
ERROR AMP GAIN
(f 0dB ) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f 0dB and 180°. The
following equations relate to the compensation network’s poles,
40
20
20LOG
(R 2 /R 1 )
20LOG
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 , and C 3 ) in
Figure 32. Use the following guidelines for locating the poles and
zeros of the compensation network.
Figure 35 shows an asymptotic plot of the Boost converter’s gain
vs frequency. Using the previously mentioned guidelines should
give a compensation gain similar to the curve plotted. The open
0
-20
-40
-60
(VO/(DV OSC *(1-D)))
MODULATOR
GAIN
F LC
10 100 1k
F RHP F ESR
10k 100k
COMPENSATION
GAIN
LOOP GAIN
1M 10M
loop error amplifier gain bounds the compensation gain. Check
the compensation gain at F P2 with the capabilities of the error
amplifier. The Loop Gain is constructed on the log-log graph of
21
FREQUENCY (Hz)
FIGURE 35. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FN7954.3
October 5, 2012
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