参数资料
| 型号： | ISL83387EIVZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | IC 3DRVR/3RCVR RS232 3V 24-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 3/3 |
| 规程： | RS232 |
| 电源电压： | 3 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
7
FN6040.1
July 8, 2005
mode an RC time constant after this rising edge. The time
constant isn’t critical, because the ISL83387E remains
powered up for 30 seconds after the FORCEON falling edge,
even if there are no signal transitions. This gives slow-to-
wake systems (e.g., a mouse) plenty of time to start
transmitting, and as long as it starts transmitting within 30
seconds both systems remain enabled.
VL Logic Supply Input
Unlike other RS-232 interface devices where the CMOS
outputs swing between 0 and VCC, the ISL83387E features
a separate logic supply input (VL; 1.8V to 5V, regardless of
VCC) that sets VOH for the receiver and INVALID outputs.
Connecting VL to a host logic supply lower than VCC,
prevents the ISL83387E outputs from forward biasing the
input diodes of a logic device powered by that lower supply.
Connecting VL to a logic supply greater than VCC ensures
that the receiver and INVALID output levels are compatible
even with the CMOS input VIH of AC, HC, and CD4000
devices. Note that the VL supply current increases to 100A
powers the transmitter and logic inputs, thereby setting their
switching thresholds to levels compatible with the logic
supply. This separate logic supply pin allows a great deal of
flexibility in interfacing to systems with different logic
supplies. If logic translation isn’t required, connect VL to the
ISL83387E VCC.
INVALID Output
The INVALID output always indicates (see Table 2) whether
or not 30
s have elapsed with invalid RS-232 signals (see
TABLE 2. POWERDOWN LOGIC TRUTH TABLE
RCVR OR XMTR
EDGE WITHIN 30
SEC?
FORCEOFF
INPUT
FORCEON
INPUT
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
RS-232 LEVEL
PRESENT AT
RECEIVER INPUT?
INVALID
OUTPUT
MODE OF OPERATION
NO
H
Active
NO
L
Normal Operation (Enhanced
Auto Powerdown Disabled)
NO
H
Active
YES
H
YES
H
L
Active
NO
L
Normal Operation (Enhanced
Auto Powerdown Enabled)
YES
H
L
Active
YES
H
NO
H
L
High-Z
Active
NO
L
Powerdown Due to Enhanced
Auto Powerdown Logic
NO
H
L
High-Z
Active
YES
H
X
L
X
High-Z
Active
NO
L
Manual Powerdown
X
L
X
High-Z
Active
YES
H
INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X
NOTE 3
Active
YES
H
Normal Operation
X
NOTE 3
High-Z
Active
NO
L
Forced Auto Powerdown
NOTES:
3. Input is connected to INVALID Output.
FIGURE 2. CONNECTIONS FOR MANUAL POWERDOWN
PWR
FORCEOFF, FORCEON
CPU
I/O
ISL83387E
MGT
LOGIC
UART
VL
I/O CHIP
POWER SUPPLY
VCC
INVALID
FIGURE 3. CIRCUIT TO ENSURE IMMEDIATE POWER UP
WHEN EXITING FORCED POWERDOWN
FORCEOFF
FORCEON
POWER
MASTER POWERDOWN LINE
1M
0.1
F
MANAGEMENT
UNIT
ISL83387E
ISL83387E
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