参数资料
型号: ISL84053IA-T
厂商: Intersil
文件页数: 5/19页
文件大小: 0K
描述: IC MUX/DEMUX TRIPLE 2X1 16QSOP
标准包装: 2,500
功能: 多路复用器/多路分解器
电路: 3 x 2:1
导通状态电阻: 225 欧姆
电压电源: 单/双电源
电压 - 电源,单路/双路(±): 2 V ~ 12 V,±2 V ~ 6 V
电流 - 电源: 1µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
ISL84051, ISL84052, ISL84053
13
FN6047.10
May 16, 2011
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 8). These additional diodes
limit the analog signal from 1V below V+ to 1V above V-. The
low leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
Power-Supply Considerations
The ISL8405x construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and GND.
V+ and V- drive the internal CMOS switches and set their
analog voltage limits, so there are no connections between the
analog signal path and GND. Unlike switches with a 13V
maximum supply voltage, the ISL8405x 15V maximum supply
voltage provides plenty of room for the 10% tolerance of 12V
supplies (±6V or 12V single supply), as well as room for
overshoot and noise spikes.
This family of switches performs equally well when operated
with bipolar or single voltage supplies. The minimum
recommended supply voltage is 2V or ±2V. It is important to
note that the input signal range, switching times, and
ON-resistance degrade at lower supply voltages. Refer to the
“Electrical Specification” tables beginning on page 5 and
“Typical Performance Curves” beginning on page 14 for
details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no affect
on logic thresholds. This switch family is TTL compatible (0.8V
and 2.4V) over a V+ supply range of 2.7V to 10V. At 12V the VIH
level is about 3.5V. This is still below the CMOS guaranteed
high output minimum level of 4V, but noise margin is reduced.
For best results with a 12V supply, use a logic family that
provides a VOH greater than 4V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past
100MHz (see Figure 17). Figure 17 also illustrates that the
frequency response is very consistent over varying analog
signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off isolation is the
resistance to this feed through, while crosstalk indicates the
amount of feed through from one switch to another. Figure 18
details the high off isolation and crosstalk rejection provided
by this family. At 10MHz, off isolation is about 55dB in 50
systems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease off
isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One of
these diodes conducts if any analog signal exceeds V+ or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given signal
pin are identical and therefore fairly well balanced, they are
reverse biased differently. Each is biased by either V+ or V- and
the analog signal. This means their leakages will vary as the
signal varies. The difference in the two diode leakages to the
V+ and V- pins constitutes the analog-signal-path leakage
current. All analog leakage current flows between each pin
and one of the supply terminals, not to the other switch
terminal. This is why both sides of a given switch can show
leakage currents of the same or opposite polarity. There is no
connection between the analog signal paths and GND.
FIGURE 8. INPUT OVERVOLTAGE PROTECTION
V-
VCOM
VNO OR NC
OPTIONAL PROTECTION
V+
LOGIC
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
1k
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