参数资料
型号: ISL84581IVZ
厂商: Intersil
文件页数: 13/15页
文件大小: 0K
描述: IC MULTIPLEXER 8X1 16TSSOP
标准包装: 960
功能: 多路复用器
电路: 1 x 8:1
导通状态电阻: 180 欧姆
电压电源: 单/双电源
电压 - 电源,单路/双路(±): 2 V ~ 12 V,±2 V ~ 6 V
电流 - 电源: 7µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
7
FN6416.3
April 13, 2009
INHIBIT Turn-OFF Time, tOFF
V+ = 3.0V, VNO = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0V to 3V (see Figure 1, Note 9)
25
-
37
50
ns
Full
-
60
ns
Address Transition Time, tTRANS
V+ = 3.0V, VNO = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0V to 3V (see Figure 1, Note 9)
25
-
96
120
ns
Full
-
145
ns
Break-Before-Make Time, tBBM
V+ = 3.6V, VNO = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0V to 3V (see Figure 3, Note 9)
Full
3
13
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2, Note 9)
25
-
0.3
1
pC
OFF-Isolation
RL = 50Ω, CL = 15pF, f = 100kHz,
VNO = 1VRMS (see Figures 4 and 18)
25
-
92
-
dB
POWER SUPPLY CHARACTERISTICS
Power Supply Range
(Note 10)
Full
2
-
12
V
NOTES:
3. VIN = Input logic voltage to configure the device in a given state.
4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5.
ΔrON = rON (MAX) - rON (MIN).
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25°C.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Limits established by characterization and are not production tested.
10. Limits should be considered typical and are not production tested.
Electrical Specifications 3.3V SupplyTest Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3),
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 4, 8) TYP
MAX
(Notes 4, 8) UNITS
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT
50%
tr < 20ns
tf < 20ns
tON
3V
0V
tOFF
LOGIC
INPUT
SWITCH
OUTPUT
90%
0V
90%
VOUT
VNO0
V
OUT
V
(NO or NC)
R
L
R
L
r
ON
+
------------------------
=
LOGIC
INPUT
VOUT
RL
COM
NO0
INH
300
Ω
35pF
GND
V-
C
NO1-NO7
CL
V+
ADDA-C
C
V+
C
ISL84581
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