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参数资料
| 型号： | ISL85033IRTZ-T7A |
| 厂商： | Intersil |
| 文件页数： | 17/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 28TQFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.8 V ~ 28 V |
| 输入电压： | 4.5 V ~ 28 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 300kHz ~ 2MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 28-TQFN（4x4） |
| 其它名称： | ISL85033IRTZ-T7ADKR ISL85033IRTZ-T7ATRDKR ISL85033IRTZ-T7ATRDKR-ND |
ISL85033
shorted to GND with VOUT1 in regulation, it will enter overcurrent
hiccup mode with a very short hiccup waiting time. The reason is
that VOUT1 is still in regulation and can pull-up SS2 very quickly
via the resistor added between VOUT1 and SS2.
C 1
0.22μF
SS1
V OUT1
C 3
5.0V
Figure 42 illustrates output sequencing. When EN1 is high and
SS2
EN2 is floating, OUT1 comes up first and OUT2 won't start until
OUT1 > 90% of its regulation point. If EN1 is floating and EN2 is
high, OUT2 comes up first and OUT1 won't start until OUT2 > 90%
of its regulation point. If EN1 = EN2 = high, OUT1 and OUT2 come
ISL85033
V OUT2
C 4
3.3V
up at the same time. Please refer to Table 1 for conditions
related to Figure 42 (Output Sequencing).
EN1
High
EN2
Floating
TABLE 1. OUTPUT SEQUENCING
V OUT1 V OUT2
First
After V OUT1 > 90%
NOTE
R 2
8.06k
R 1
25.5k
Floating
High
High
High
After V OUT2 > 90%
Same time
First
Same time
FIGURE 41. ABSOLUTE START-UP
Floating Floating
as V OUT2
as V OUT1
Not
Allowed
SS1
V OUT1
5.0V
C1
0.1μF
SS1
SS2
V OUT1
C 3
5.0V
C 1
0.1μF
C 2
0.1μF
SS2
EN1
EN2
ISL85033
V OUT2
C 3
C 4
3.3V
C2
0.22μF
ISL85033
V OUT2
C 4
3.3V
FIGURE 42. OUTPUT SEQUENCING
FIGURE 39. INDEPENDENT START-UP
Protection Features
The ISL85033 limits the current in all on-chip power devices.
Overcurrent protection limits the current on the two buck
C 1
0.1μF
C 2
0.1μF
SS1
SS2
V OUT1
ISL85033
V OUT2
C 3
C 4
5.0V
3.3V
regulators and internal LDO for V CC .
Buck Regulator Overcurrent Protection
During the PWM on-time, the current through the internal
switching MOSFET is sampled and scaled through an internal
pilot device. The sampled current is compared to a nominal 5A
overcurrent limit. If the sampled current exceeds the overcurrent
limit reference level, an internal overcurrent fault counter is set
to 1 and an internal flag is set. The internal power MOSFET is
immediately turned off and will not be turned on again until the
next switching cycle.
The protection circuitry continues to monitor the current and
FIGURE 40. RATIOMETRIC START-UP
17
turns off the internal MOSFET as described. If the overcurrent
condition persists for 17 sequential clock cycles, the overcurrent
fault counter overflows indicating an overcurrent fault condition
exists. The regulator is shut down and power-good goes low.
The buck controller attempts to recover from the overcurrent
condition after waiting 8 soft-start cycles. The internal
overcurrent flag and counter are reset. A normal soft-start cycle
is attempted and normal operation continues if the fault
FN6676.6
February 23, 2012
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