参数资料
型号: ISL8701AIBZ
厂商: Intersil
文件页数: 7/12页
文件大小: 0K
描述: IC SEQUENCER QUAD ADJ 14-SOIC
标准包装: 50
类型: 序列发生器
监视电压数目: 4
输出: 开路漏极或开路集电极
复位: 高有效/低有效
复位超时: 可调节/可选择
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOICN
包装: 管件
产品目录页面: 1244 (CN2011-ZH PDF)
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
OVERVOLTAGE
LIMIT
UNDERVOLTAGE
<t FLTH
t FLTH
t FLTL
LIMIT
MONITORED VOLTAGE
t FLTL
t FLTH
RAMPING UP AND DOWN
FAULT OUTPUT
FIGURE 3. ISL8702A, ISL8703A, ISL8704A, ISL8705A FAULT OPERATIONAL DIAGRAM
Typical Performance Curves
1.208
310
1.207
1.206
1.205
290
270
V IN = 24V
1.204
1.203
V IN = 2.5V
V IN = 12V
250
230
V IN = 12V
1.202
210
1.201
1.200
1.199
1.198
V IN = 24V
190
170
150
V IN = 2.5V
-40
-10
0
25
60
85
100
-40
-10
0
25
60
85
100
TEMP (°C)
FIGURE 4. UV/OV RISING THRESHOLD
Applications Usage
Using the ISL870XAEVAL1 Platform
The ISL870XAEVAL1 platform is the primary evaluation
board for this family of sequencers. See Figure 16 for
photograph and schematic.The evaluation board is shipped
with an ISL8702A mounted in the left position and with the
other device variants loose packed. In the following
discussion, test points names are bold on initial occurrence
for identification.
The V IN test point is the chip bias and can be biased from
3.3V to 24V. The VHI test point is for the ENABLE and
FAULT pull-up voltage which are limited to a maximum of
24V independent of V IN . The UV/OV resistor divider is set so
that a nominal 12V on the VMONITOR test point is compliant
and with a rising OV set at 13.2V and a falling UV set at
10.7V. These three test points (V IN ,VHI and VMONITOR)
are brought out separately for maximum flexibility in
evaluation.
VMONITOR ramping up and down through the UV and OV
levels will result in the FAULT output signaling the out of
bound conditions by being released to pull high to the VHI
voltage as shown in Figures 6 and 7.
7
TEMP (°C)
FIGURE 5. V IN CURRENT
Once the voltage monitoring FAULT is resolved and where
applicable, the SEQ_EN (#) is satisfied, sequencing of the
ENABLE_X(#) outputs begins. When sequence enabled the
ENABLE_A , ENABLE_B , ENABLE_C and lastly
ENABLE_D are asserted in that order and when SEQ_EN is
disabled the order is reversed. See Figures 8 and 9
demonstrating the sequenced enabling and disabling of the
ENABLE outputs. The timing between ENABLE outputs is
set by the resistor values on the TB, TC, TD pins as shown.
Figure 10 illustrates the timing from either SEQ_EN and/or
VMONITOR being valid to ENABLE_A being asserted with a
10nF TIME capacitor. Figure 11 shows that ENABLE_X
outputs are pulled low even before V IN = 1V. This is critical
to ensure that a false enable is not signaled. Figure 12
illustrates the SEQ_EN# input disabling and enabling the
ISL8705A ENABLE# outputs. Notice the reversal in order
and delay timing from ENABLE_X# to ENABLE_X#.
Figure 13 shows the time from SEQ_EN transition with the
voltage ramping across the TIME capacitor to TIME Vth
being met. This results in the immediate pull down of the
TIME pin and simultaneous ENABLE_A enabling.
FN6381.0
October 12, 2006
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ISL8701IBZ 功能描述:监控电路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟(典型值):10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel
ISL8701IBZ-T 功能描述:监控电路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟(典型值):10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel
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