参数资料
型号: ISL8723IRZ
厂商: Intersil
文件页数: 2/14页
文件大小: 0K
描述: IC POWER SUPPLY SEQUENCER 24QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 75
应用: 电源序列发生器
电源电压: 2.5 V ~ 5 V
电流 - 电源: 480µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN 裸露焊盘(4x4)
包装: 管件
产品目录页面: 1244 (CN2011-ZH PDF)
ISL8723, ISL8724
AIN
AOUT
BIN
BOUT
VDD
BIAS
LOCK OUT
VDD+5V
Q-PUMP
DIN
CIN
V DD
ENABLE
UVLO_A
COUT
DOUT
1μA
DLY_ONX
10μA
SYSRST
UVLO_B
UVLO_C
1.26V
1μA
-10μA
RESET
UVLO_D
GROUND
DLY_OFFX
10ms
RISING DELAY
1.26V
FIGURE 1. TYPICAL ISL8723 APPLICATION
USAGE
30μs
FILTER
UVLOX
0.633V
LOGIC
150ms
GATEX
RESET
RISING DELAY
EN
SYSRST
FIGURE 2. ISL8723 BLOCK DIAGRAM (1/4)
Pin Descriptions
PIN
PIN
#
23
10, 19
NAME
VDD
GND
FUNCTION
Chip Bias
Bias Return
Bias IC from nominal 2.5V to 5V
IC ground.
DESCRIPTION
NOTE: Pin 19 internally tied to GND with 6k Ω . This pin can be tied to GND or left open.
1
24
ENABLE/
ENABLE
RESET
Input to start on/off
sequencing
RESET Output
Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is
disabled for 10ms after UVLO is satisfied. ISL8723 has ENABLE. ISL8724 has ENABLE.
RESET provides a high signal ~160ms after all GATEs are fully enhanced. This delay is for stabilization
of output voltages. RESET will assert low upon any UVLO not being satisfied or ENABLE/ENABLE being
deasserted. The RESET output is an open drain N-channel FET and is guaranteed to be in the correct
state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X.
20
12
17
14
21
8
16
15
UVLO_A
UVLO_B
UVLO_C
UVLO_D
DLY_ON_A
DLY_ON_B
DLY_ON_C
DLY_ON_D
Undervoltage Lock
Out/Monitoring
Input
Gate On Delay
Timer Output
2
These inputs provide for a programmable UV lockout referenced to an internal 0.631V reference and
are filtered to ignore short (<7μs) transients below programmed UVLO level.
Allows for programming the delay and sequence for V OUT turn-on using a capacitor to ground. Each
cap is charged with 1μA, 10ms after turn-on initiated by ENABLE/ENABLE with an internal current
source providing delayed enhancement of the associated FETs GATE to turn-on.
FN6413.1
April 22, 2009
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