参数资料
型号: ISL88012EVAL1Z
厂商: Intersil
文件页数: 10/14页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL88012
产品培训模块: Solutions for Industrial Control Applications
标准包装: 1
主要目的: 电源管理,电源监控器/跟踪器/序列发生器
嵌入式:
已用 IC / 零件: ISL88012
已供物品:
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Manual Reset
The manual reset input (MR) allows the user to trigger a
reset by using a push-button switch. The MR input is an
active-low debounced input. By connecting a push-button
directly from MR to ground, the designer adds manual
system reset capability (see Figure 4). Reset is asserted if
the MR pin is pulled low to less than 100mV for 1 μ s or longer
while the push-button is closed. After MR is released, the
reset outputs remain asserted for t POR (200ms) and then
released.
V DD
Watchdog Timer
The Watchdog Timer circuit checks microprocessor activity
by monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within t WDT (1.6s nominal),
otherwise the reset signal is asserted (see Figure 5).
Internally, the 1.6s timer is cleared by either a reset or by
toggling the WDI input.
Besides the 1.6s default timeout during normal operation,
these devices also have a longer 51s timeout for start-up.
During this time, a reset cannot be asserted due to the WDI
not being toggled. The longer delay at power-on allows an
operating system to boot, an FPGA to initialize, or the
system software to initialize without the burden of dealing
ISL88011
ISL88012
ISL88013
ISL88014
R pu
RST/MR
with the Watchdog.
Symbol Table
ISL88015
PB
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
V THVDD
V DD
1V
START t WDT
<t WDT
<t WDT
STARTt WDT
t WDT
WDI
>t WDPS
RST
t POR
t POR
RST
FIGURE 5. WATCHDOG TIMING DIAGRAM
10
FN8093.4
June 13, 2013
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