参数资料
型号: ISL88013EVAL1Z
厂商: Intersil
文件页数: 8/14页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL88013
产品培训模块: Solutions for Industrial Control Applications
标准包装: 1
主要目的: 电源管理,电源监控器/跟踪器/序列发生器
嵌入式:
已用 IC / 零件: ISL88013
已供物品:
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Pin Description
RST
The push-pull RST output is set to V DD (HIGH) listed in the
following:
ensure that the power supply has stabilized. Thereafter,
reset is again asserted whenever V DD falls below V THVDD .
The device is designed with hysteresis to help prevent
chattering due to noise.
1. The device is first powered up.
2. Either V DD or the voltage on VMON falls below their
respective minimum voltage sense levels.
3. MR is asserted.
4. The watchdog timeout expires.
RST/MR
This pin functions as both a reset output and a manual reset
input. The RST output functions identically to the
complementary RST output but is an open drain output that
is pulled to GND (LOW) when reset is asserted. The MR
input is an active-low debounced input to which a user can
connect a push-button to add manual reset capability or
drive with active low signal from a controller.
V DD
The V DD pin is the power supply terminal. It is monitored by
the ISL88011, ISL88012 and ISL88013. For these devices,
the voltage at this pin is compared against an internal
factory-programmed voltage trip point, V THVDD . A reset is
VMON
The VMON pin on the ISL88012, ISL88014 and ISL88015 is
a monitored input voltage that is user-adjustable. The
voltage at this pin is compared against an internal 600mV
reference voltage (V THVMON ) and a reset is asserted
whenever the monitored voltage falls below this trip point.
WDI
The Watchdog Input takes an input from a microprocessor
and ensures that it periodically toggles the WDI pin,
otherwise the internal watchdog timer runs out and reset is
asserted. The internal Watchdog Timer is cleared whenever
the WDI input pin sees a rising or falling edge or the device
is manually reset.
C POR
The C POR input pin lets users increase the Power-On Reset
timeout delay (t POR ) by connecting a capacitor between
C POR and ground. (See Figure 3)
first asserted when the device is initially powered up to
V THVDD
V DD
1V
V THVMON
VMON
>t MR
MR
t POR
t RPD
t POR
t RPD
t POR
t POR
RST
RST
FIGURE 1. VOLTAGE MONITORING TIMING DIAGRAM
8
FN8093.4
June 13, 2013
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