参数资料
型号: ISL88016IHTZ-T
厂商: Intersil
文件页数: 5/7页
文件大小: 0K
描述: IC VOLTAGE SUPERVISOR TSOT23-6
产品培训模块: Solutions for Industrial Control Applications
标准包装: 3,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-6 细型,TSOT-23-6
供应商设备封装: TSOT-23-6
包装: 带卷 (TR)
ISL88016, ISL88017
V TH / V POR
V DD
1V
t POR
t RST
t POR
t POR
RST
MR
>t MR
FIGURE 1. VOLTAGE MONITORING TIMING DIAGRAM
Principles of Operation
The ISL88016 and ISL88017 devices provides a low cost
solution for those voltage monitoring applications needing
RST/MR
ISL88016
V DD
supply voltage supervision with power reset control, and
GND
ISL88017
VSET3
manual reset assertion. By integrating these common
features along with three pins of Vth programming into a
small 6 Ld TSOT-23 package and using only 1μA of supply
VSET1
VSET2
current, the ISL88016 and ISL88017 devices can lower
system cost, reduce board space requirements, and
increase the reliability of a system while reducing inventory
overhead costs.
Low Voltage Monitoring
During normal operation, the ISL88016 and ISL88017
monitor the voltage level of V DD . The device asserts a reset
(RST = LOW) if this voltage is less than the programmed
voltage trip point. The reset signal prevents system
operation during a power failure or brownout condition. This
reset signal remains asserted until V DD exceeds the voltage
threshold setting for the reset time delay period t POR . (See
Figure 1).
The ISL88016 and ISL88017 allow users to customize the
Power-On Reset voltage threshold level, which is the voltage
at which the reset is deasserted. The three VSET inputs are
either tied to V DD , GND or left open to program V TH . See
the Power-On Reset Voltage Setting table on page 3 for
specific voltage configuration. Also see Figure 2 for a
schematic representation of the VSET pins being
programmed, noting the minimum necessary components
for IC operation. Do not attempt to reprogram a V TH while
the IC is biased.
5
FIGURE 2. SETTING V POR USING VSET INPUTS
Power-On Reset (POR)
Applying power to the ISL88016 and ISL88017 activates a
POR circuit which asserts reset once V DD = 1 V. (i.e., RST
goes LOW). This provides several benefits:
? It prevents the system microprocessor from starting to
operate with insufficient voltage.
? It prevents the processor from operating prior to
stabilization of the oscillator.
? It ensures that the monitored device is held out of
operation until internal registers are properly loaded.
? It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
The reset signal remains asserted until V DD rises above the
minimum voltage sense level for time period t POR . This
ensures that the V DD voltage has stabilized.
Optional V DD de-coupling capacitance can be added to filter
transients if needed.
FN6141.0
December 22, 2006
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