参数资料
型号: ISL88042EVAL1Z
厂商: Intersil
文件页数: 5/8页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL88042
标准包装: 1
系列: *
ISL88042
point to some other voltage above 600mV according to
Equation 1:
V TRIP = 0.6V × R 1 + R 2 / R 2
(EQ. 1)
The reset signal remains active until V DD rises above the
minimum voltage sense level for time period t POR . This
ensures that the supply voltage has stabilized to sufficient
operating levels.
Power-On Reset (POR)
Applying power to the ISL88042 activates a POR circuit, which
makes the reset pin(s) active (i.e. RST goes high while RST
goes low). These signals provide several benefits:
? They prevent the system microprocessor from starting to
operate with insufficient voltage.
? They prevent the processor from operating prior to
stabilization of the oscillator.
? They ensure that the monitored device is held out of
operation until internal registers are properly loaded.
? They allow time for an FPGA to download its configuration
prior to initialization of the circuit.
V TH1/ V TH2
V DD /
Manual Reset
The manual-reset input (MR) allows the user to trigger a reset
by using a push-button switch or by signaling the input low. The
MR input is an active low debounced input. Reset is asserted if
the MR pin is pulled low to less than 100mV for the minimum
MR pulse width or longer while the push-button is closed. After
MR is released, the reset output remains asserted low for t POR
(200ms) and then is released.
Figures 2 and 3 illustrate the ISL88042’s operation.
V2MON
MR
1V
>t MR
t POR
t RPD
t POR
t POR
RST
>t MD
FIGURE 2. POWER SUPPLY MONITORING DIAGRAM
VXMON
V TH
t RPD
t POR
RST
FIGURE 3. VOLTAGE MONITORING DIAGRAM
5
FN6655.2
July 26, 2010
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