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| 型号： | ISL8840AMUZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/15页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK ISO 8MSOP |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 100% |
| 电源电压： | 9 V ~ 30 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -55°C ~ 125°C |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 包装： | 带卷 (TR) |
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is in Equation 6.
Fm = --------------------
1
SnTsw
(EQ. 6)
VREF
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
D1
R1
COMP
the modulator gain becomes:
Fm = --------------------------------------- = ----------------------------
m c SnTsw
C1
Q1
GND
1 1
( Sn + Se ) Tsw
(EQ. 7)
where Se is slope of the external ramp and
m c = 1 + -------
Se
Sn
(EQ. 8)
FIGURE 5. SOFT-START
The criteria for determining the correct amount of external
The COMP pin is clamped to the voltage on capacitor C1
plus a base-emitter junction by transistor Q1. C1 is charged
from VREF through resistor R1 and the base current of Q1.
At power-up C1 is fully discharged, COMP is at ~0.7V, and
the duty cycle is zero. As C1 charges, the voltage on COMP
increases, and the duty cycle increases in proportion to the
ramp can be determined by appropriately setting the
damping factor of the double-pole located at the switching
frequency. The double-pole will be critically damped if the
Q-factor is set to 1, over-damped for Q < 1, and
under-damped for Q > 1. An under-damped condition may
result in current loop instability.
Q = -------------------------------------------------
voltage on C1. When COMP reaches the steady state
operating point, the control loop takes over and soft start is
complete. C1 continues to charge up to VREF and no longer
1
π ( m c ( 1 – D ) – 0.5 )
(EQ. 9)
affects COMP. During power down, diode D1 quickly
discharges C1 so that the soft start circuit is properly
where D is the percent of on time during a switching cycle.
Setting Q = 1 and solving for Se yields
S e = S n ? ? --- + 0.5 ? ------------- – 1 ?
initialized prior to the next power on sequence.
Gate Drive
The ISL884xA is capable of sourcing and sinking 1A peak
1 1
? ? π ? 1 – D ?
(EQ. 10)
current. To limit the peak current through the IC, an optional
external resistor may be placed between the totem-pole
output of the IC (OUT pin) and the gate of the MOSFET. This
Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by t ON to obtain the voltage change that occurs during t ON .
V e = V n ? ? --- + 0.5 ? ------------- – 1 ?
small series resistor also damps any oscillations caused by
the resonant tank of the parasitic inductances in the traces of
the board and the FET’s input capacitance.
1 1
? ? π ? 1 – D ?
(EQ. 11)
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
where Vn is the change in the current feedback signal ( Δ I)
during the on time and Ve is the voltage that must be added
by the external ramp.
For a flyback converter, Vn can be solved for in terms of
input voltage, current transducer components, and primary
inductance, yielding
V e = ---------------------------------------------------- ? ? --- + 0.5 ? ------------- – 1 ?
? ? π ? 1 – D ?
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability.
D ? T SW ? V IN ? R CS 1 1
L p
V
(EQ. 12)
Slope compensation may be accomplished by summing an
external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback
error signal. Adding the external ramp to the current
feedback signal is the more popular method.
11
where R CS is the current sense resistor, f sw is the switching
frequency, L p is the primary inductance, V IN is the minimum
input voltage, and D is the maximum duty cycle.
FN6320.3
April 18, 2007
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| ISL8841AABZ | 功能描述:IC REG CTRLR BST FLYBK ISO 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8841AABZ-T | 功能描述:IC REG CTRLR BST FLYBK ISO 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 特色产品:LM3753/54 Scalable 2-Phase Synchronous Buck Controllers 标准包装:1 系列:PowerWise® PWM 型:电压模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.5 V ~ 18 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-5°C ~ 125°C 封装/外壳:32-WFQFN 裸露焊盘 包装:Digi-Reel® 产品目录页面:1303 (CN2011-ZH PDF) 其它名称:LM3754SQDKR |
| ISL8841AAUZ | 功能描述:IC REG CTRLR BST FLYBK ISO 8MSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8841AAUZ-T | 功能描述:IC REG CTRLR BST FLYBK ISO 8MSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8841AMBEP | 制造商:Intersil Corporation 功能描述:CURRENT MODE PWM CNTRLR 1A 8SOIC N - Rail/Tube |
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