参数资料
| 型号： | ISL88550AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 20/25页 |
| 文件大小： | 0K |
| 描述： | IC PWM CONTROLLER 28TQFN |
| 标准包装： | 6,000 |
| 应用： | PWM 控制器 |
| 输入电压： | 2 V ~ 25 V |
| 电流 - 电源： | 25µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
ISL88550A
spuriously turn on because of dV/dt caused by high-side
MOSFET turning on, as this would result in shoot through
current degrading the efficiency. MOSFETs with a lower
where R UGATE is the high-side MOSFET driver ’s
ON-resistance (1.5 Ω typical) and R GATE is the internal gate
resistance of the MOSFET (~2 Ω ) :
Q GD to Q GS ratio have higher immunity to dV/dt.
For proper thermal-management design, calculate the power
P HSDR = Q G × V GS × f SW ×
R GATE
R GATE + R UGATE
(EQ. 22)
dissipation at the desired maximum operating junction
temperature, maximum output current, and worst-case input
voltage (for low-side MOSFET, worst case is at V IN(MAX) ; for
high-side MOSFET, it could be either at V IN(MIN) or
V IN(MAX) ). The high-side MOSFET and low-side MOSFET
have different loss components due to the circuit operation.
The low-side MOSFET operates as a zero voltage switch;
therefore, major losses are:
1. The channel conduction loss (P LSCC )
2. The body diode conduction loss (P LSDC )
3. The gate-drive loss (P LSDR )
where V GS = V DD = 5V. In addition to the losses in
Equation 22, allow about 20% more for additional losses
because of MOSFET output capacitances and low-side
MOSFET body-diode reverse recovery charge dissipated in
the high-side MOSFET that is not well defined in the
MOSFET data sheet. Refer to the MOSFET data sheet for
thermal-resistance specifications to calculate the PC board
area needed to maintain the desired maximum operating
junction temperature with the above-calculated power
dissipations. To reduce EMI caused by switching noise, add
a 0.1μF ceramic capacitor from the high-side switch drain to
the low-side switch source, or add resistors in series with
P LSCC = ? ? 1 ? OUT
? ? × I LOAD 2 × r DS ( ON )
? V
? V IN
?
?
(EQ. 16)
UGATE and LGATE to slow down the switching transitions.
Adding series resistors increases the power dissipation of
P LSDC = 2 I LOAD × V F × t DT × f SW
(EQ. 17)
the MOSFET, so ensure that this does not overheat the
MOSFET.
where VF is the body-diode forward-voltage drop, t DT is the
dead time (~30ns), and f SW is the switching frequency.
Because of the zero-voltage switch operation, the low-side
MOSFET gate-drive loss occurs as a result of charging and
discharging the input capacitance, (CISS). This loss is
distributed among the average LGATE driver ’s pull-up and
pull-down resistance, RLGATE (1 Ω ), and the internal gate
resistance (RGATE) of the MOSFET (~2 Ω ). The driver
MOSFET Snubber Circuit (Buck)
Fast switching transitions cause ringing because of
resonating circuit parasitic inductance and capacitance at
the switching nodes. This high-frequency ringing occurs at
PHASE’s rising and falling transitions and can interfere with
circuit performance and generate EMI. A series R-C snubber
may be added across the lower MOSFET to dampen this
ringing. Following is the procedure for selecting the value of
the series RC circuit:
P LSDR = C ISS × V GS 2 × f SW ×
R GATE
R GATE + R LGATE
(EQ. 18)
1. Connect a scope probe to measure PHASE to GND, and
observe the ringing frequency, f R .
The high-side MOSFET operates as a duty-cycle control
switch and has the following major losses: the channel
conduction loss (P HSCC ), the VI overlapping switching loss
(P HSSW ), and the drive loss (P HSDR ). The high-side
MOSFET does not have body-diode conduction loss
because the diode never conducts current:
2. Find the capacitor value (connected from PHASE to
GND) that reduces the ringing frequency by half.
The circuit parasitic capacitance (C PAR ) at PHASE is then
equal to 1/3 the value of the added capacitance above. The
circuit parasitic inductance (L PAR ) is calculated using
Equation 23:
P HSCC =
V OUT
V IN
× I LOAD 2 × r DS ( ON )
(EQ. 19)
L PAR =
1
( 2 π × f R ) 2 × C PAR
(EQ. 23)
Q GS + Q GD
Use r DS(ON) at T J(MAX) .
P HSSW = V IN × I LOAD × f SW ×
I GATE
(EQ. 20)
The resistor for critical dampening (R SNUB ) is equal to
2 π × ?R x L PAR . Adjust the resistor value up or down to tailor
the desired damping and the peak voltage excursion. The
capacitor (C SNUB ) should be at least 2x to 4x the value of
where I GATE is the average UGATE driver output-current
determined by Equation 21:
the C PAR in order to be effective. The power loss of the
snubber circuit (P RSNUB ) is dissipated in the resistor and
I GATE ( ON ) =
2 . 5 V
R UGATE + R GATE
(EQ. 21)
P RSNUB = C SNUB × V IN 2 × f SW
(EQ. 24)
where V IN is the input voltage and f SW is the switching
frequency. Choose an R SNUB power rating that meets the
specific application’s derating rule for the power dissipation
calculated.
20
FN6168.3
April 23, 2008
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