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| 型号： | ISL88706IB831Z-TK |
| 厂商： | Intersil |
| 文件页数： | 7/15页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 3.09V 8-SOIC |
| 产品培训模块： | Voltage Supervisors |
| 标准包装： | 1 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 3.09V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 其它名称： | ISL88706IB831Z-TKDKR |
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
V TH1
V DD
1V
>t MR
MR
t POR
t RPD
t POR
t POR
RST
RST
FIGURE 1. POWER-SUPPLY MONITORING TIMING DIAGRAM (WDI TRI-STATED)
Low Voltage Monitoring
These devices monitor both the voltage level of V DD and an
auxiliary voltage on PFI.
.
R 1
When IC is initially biased reset is asserted until the V DD
voltage is greater than the specific IC fixed-voltage trip point
V IN
R 2
PFI
Power Failure Monitor
PFI V TH = 1.25 ? --------------------- ?
for the t POR duration of 200ms. At any subsequent time that
V DD does not exceed its voltage threshold, reset is once
again asserted, i.e. RST is high and RST is low (see
Figure 1).
.
These devices also have a Power-Failure Monitor that helps
to monitor an additional critical voltage on the Power-Fail
Input (PFI) pin. For example, the PFI pin could be used to
provide an early power-fail warning, detect a low-battery
condition, presence detection or simply monitor a power
supply other than +5V. The 1.25V threshold detector can be
adjusted using an external resistor divider network to provide
custom voltage monitoring of voltages greater than 1.25V,
according to Equation 1 (see Figure 2).
? R 1 + R 2 ?
(EQ. 1)
? R 2 ?
PFO goes low whenever PFI is less than the 1.25V (or
user-set) threshold voltage.
7
ISL8870x
FIGURE 2. CUSTOM V TH WITH RESISTOR DIVIDER ON PFI
If using a voltage divider on the PFI input to critique an
external voltage and intending to use the MR input to initiate
resets then avoid having the PFI voltage less than PFI Vth
+2.2V as unintended PFO transition may occur when MR is
transitioning high.
Adjusting t POR
On the ISL88707 and ISL88708, users can adjust the
Power-On Reset time-out delay (t POR ) to many times the
nominal t POR of 200ms. To do this, connect a capacitor
between C POR and ground (see Figure 3). For example,
connecting a 50pF capacitor to CPOR will increase t POR from
200ms to ~1.4s. Care should be taken in PCB layout and
capacitor placement in order to reduce stray capacitance as
much as possible, which contributes to t POR error.
FN8092.5
January 12, 2009
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