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参数资料
| 型号： | ISL88706IP826Z |
| 厂商： | Intersil |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 2.63V 8-PDIP |
| 标准包装： | 50 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 2.63V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Bipolar Voltage Sensing
Any of the ISL88705, ISL88706, ISL88707, ISL88708,
ISL88716, ISL88813 devices can be used to sense and
report the presence of both a positive and negative voltage
via the PFI and PFO, as shown in Figure 16. The V DD
monitors the positive voltage as normal and the PFI monitors
the presence of the negative supply. As the differential
voltage across the R 1 , R 2 divider is increased, the resistor
values must be chosen such that the PFI node is <1.25V
when the -V supply is satisfactory and the positive supply is
at its maximum specified value. This allows the positive
supply to fluctuate within its acceptable range without
signaling a reset. Driving the MR with the inverted PFO
signal as shown provides for reset generation when -V is not
satisfactorily present. Reset will remain asserted as long as
PFO is high.
+5V
Special Application Considerations
Using good decoupling practices will prevent transients
(i.e., due to switching noises and short duration droops in the
supply voltage) from causing unwanted resets.
When using the C POR pin, avoid stray capacitance during
layout as much as possible in order to minimize its effect on
the t POR timing.
If using a voltage resistor divider on the PFI input to critique
an external voltage and intending to use the MR input to
initiate resets then avoid having the PFI voltage less than
PFI Vth +2.2V as unintended PFO transition may occur
when MR is transitioning high.
R1
PFI
V DD
MR
PFO
100k
100k
2N3904
R2
RST
-5V
ISL8870x, ISL88716, ISL88813
RESET
V+
V-
FIGURE 16. ±5V MONITORING
12
FN8092.5
January 12, 2009
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